Keil Logo Arm Logo
Products Download Events Support Videos

Technical Support

On-Line Manuals

Assembler Reference

Conventions and feedback Assembler command line options ARM and Thumb Instructions Instruction summary Instruction width specifiers Memory access instructions General data processing instructions Flexible second operand (Operand2) Operand2 as a constant Operand2 as a register with optional shift Shift operations Multiply instructions Saturating instructions Parallel instructions Parallel add and subtract Packing and unpacking instructions Branch and control instructions Coprocessor instructions Miscellaneous instructions ThumbEE instructions Pseudo-instructions Condition codes ADD, SUB, RSB, ADC, SBC, and RSC ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND, ORR, EOR, BIC, and ORN ASR, LSL, LSR, ROR, and RRX B, BL, BX, BLX, and BXJ BFC and BFI BKPT CBZ and CBNZ CDP and CDP2 CHKA CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB, DSB, and ISB ENTERX and LEAVEX ERET HB, HBL, HBLP, and HBP IT LDC, LDC2, STC, and STC2 LDM and STM LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR, unprivileged LDR (PC-relative) LDR (register-relative) LDR pseudo-instruction LDREX and STREX MAR and MRA MCR, MCR2, MCRR, and MCRR2 MIA, MIAPH, and MIAxy MOV and MVN MOV32 pseudo--instruction MOVT MRC, MRC2, MRRC and MRRC2 MRS (system coprocessor register to ARM register) MRS (PSR to general-purpose register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL, MLA, and MLS NEG pseudo-instruction PKHBT and PKHTB PLD, PLDW, and PLI PUSH and POP QADD, QSUB, QDADD, and QDSUB REV, REV16, REVSH, and RBIT RFE SBFX and UBFX SDIV and UDIV SEL SETEND SEV, WFE, WFI, and YIELD SMC NOP SMLAD and SMLSD SMLALxy SMLALD and SMLSLD SMMUL, SMMLA, and SMMLS SMUAD{X} and SMUSD{X} SMULxy and SMLAxy SMULWy and SMLAWy SRS SSAT and USAT SSAT16 and USAT16 SUBS pc, lr SVC SWP and SWPB SXT, SXTA, UXT, and UXTA SYS TBB and TBH TST and TEQ UMULL, UMLAL, SMULL, and SMLAL UMAAL UND pseudo-instruction USAD8 and USADA8 VFP Programming Directives Reference

Assembler Reference

B, BL, BX, BLX, and BXJ

ARM Compiler toolchain v5.02 for µVision Assembler Reference
Home > ARM and Thumb Instructions > B, BL, BX, BLX, and BXJ

B, BL, BX, BLX, and BXJ

Branch, Branch with Link, Branch and exchange instruction set, Branch with Link and exchange instruction set, Branch and change to Jazelle state.

Show/hideSyntax

op1{cond}{.W} label

op2{cond} Rm

where:

op1

is one of:

B

Branch.

BL

Branch with link.

BLX

Branch with link, and exchange instruction set.

op2

is one of:

BX

Branch and exchange instruction set.

BLX

Branch with link, and exchange instruction set.

BXJ

Branch, and change to Jazelle execution.

cond

is an optional condition code. cond is not available on all forms of this instruction.

.W

is an optional instruction width specifier to force the use of a 32-bit B instruction in 32-bit Thumb.

label

is a PC-relative expression.

Rm

is a register containing an address to branch to.

Show/hideOperation

All these instructions cause a branch to label, or to the address contained in Rm. In addition:

  • The BL and BLX instructions copy the address of the next instruction into LR (R14, the link register).

  • The BX and BLX instructions can change the processor state from ARM to Thumb, or from Thumb to ARM.

    BLX label always changes the state.

    BX Rm and BLX Rm derive the target state from bit[0] of Rm:

    • if bit[0] of Rm is 0, the processor changes to, or remains in, ARM state

    • if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.

  • The BXJ instruction changes the processor state to Jazelle.

Show/hideInstruction availability and branch ranges

Table 8 shows the instructions that are available in ARM and Thumb state. Instructions that are not shown in this table are not available. Notes in brackets show the first architecture version where the instruction is available.

Table 8. Branch instruction availability and range

InstructionARM 16-bit Thumb32-bit Thumb
B label±32MB(All)±2KB(All T)±16MB[a](All T2)
B{cond} label±32MB(All)-252 to +258(All T)±1MBa(All T2)
BL label±32MB(All)±4MB [b](All T)±16MB(All T2)
BL{cond} label±32MB(All)- --
BX Rm [c]Available(4T, 5)Available(All T)Use 16-bit(All T2)
BX{cond} Rm [c]Available(4T, 5)- --
BLX label±32MB(5)±4MB [b](5T)±16MB(All T2 except ARMv7-M)
BLX RmAvailable(5)Available(5T)Use 16-bit(All T2)
BLX{cond} RmAvailable(5)- --
BXJ RmAvailable(5J, 6)- Available(All T2 except ARMv7-M)
BXJ{cond} RmAvailable(5J, 6)- --

[a] Use .W to instruct the assembler to use this 32-bit instruction.

[b] This is an instruction pair.

[c] The assembler accepts BX{cond} Rm for code assembled for ARMv4 and converts it to MOV{cond} PC, Rm at link time, unless objects targeted for ARMv4T are present.


Show/hideExtending branch ranges

Machine-level B and BL instructions have restricted ranges from the address of the current instruction. However, you can use these instructions even if label is out of range. Often you do not know where the linker places label. When necessary, the linker adds code to enable longer branches. The added code is called a veneer.

Show/hideB in Thumb

You can use the .W width specifier to force B to generate a 32-bit instruction in Thumb code.

B.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit instruction.

For forward references, B without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb instruction.

Show/hideBX, BLX, and BXJ in ThumbEE

These instructions can be used as branches in ThumbEE code, but cannot be used to change state. You cannot use the op{cond} label form of these instructions in ThumbEE. In the register form, bit[0] of Rm must be 1, and execution continues at the target address in ThumbEE state.

Note

BXJ behaves like BX in ThumbEE.

Show/hideRegister restrictions

You can use PC for Rm in the ARM BX instruction, but this is deprecated in ARMv6T2 and above. You cannot use PC in other ARM instructions.

You can use PC for Rm in the Thumb BX instruction. You cannot use PC in other Thumb instructions.

You can use SP for Rm in these ARM instructions but these are deprecated in ARMv6T2 and above.

You can use SP for Rm in the Thumb BX and BLX instructions, but these are deprecated. You cannot use SP in the other Thumb instructions.

Show/hideCondition flags

These instructions do not change the flags.

Show/hideArchitectures

See Table 8 for details of availability of these instructions in each architecture.

Show/hideExamples

    B       loopA
    BLE     ng+8
    BL      subC
    BLLT    rtX
    BEQ     {PC}+4  ; #0x8004

Show/hideSee also

Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
Non-ConfidentialID062912
PDF file icon  PDF version
Home > ARM and Thumb Instructions > B, BL, BX, BLX, and BXJ

Products

Development Tools

 

Hardware & Collateral

Downloads

Support

Buy

arm-logo-small

Contact Us | Site Feedback | Terms of Use | Privacy Policy

Copyright © 2013 ARM Ltd and ARM Germany GmbH. All rights reserved.

 Keil logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.