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SMULWy and SMLAWy
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| Home > ARM and Thumb Instructions > SMULWy and SMLAWy | |||
Signed Multiply Wide and Signed Multiply-Accumulate Wide, with one 32-bit and one 16-bit operand, providing the top 32-bits of the result.
SyntaxSMULW<y>{cond} {Rd},Rn,Rm
SMLAW<y>{cond}Rd,Rn,Rm,Ra
where:
<y>is either
BorT.Bmeans use the bottom half (bits [15:0]) ofRmTmeans use the top half (bits [31:16]) ofRmcondis an optional condition code.
Rdis the destination register.
Rn, Rmare the registers holding the values to be multiplied.
Rais the register holding the value to be added.
SMULWy multiplies the signed integer from the
selected half of RmRnRd
SMLAWy multiplies the signed integer from the
selected half of RmRnRaRd
You cannot use PC for any register.
You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
These instructions do not affect the N, Z, C, or V flags.
If overflow occurs in the accumulation, SMLAWy sets
the Q flag.
These ARM instructions are available in ARMv6 and above, and E variants of ARMv5T.
These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.
There are no 16-bit Thumb versions of these instructions.
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
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