|
|||
| Products Download Events Support Videos | |||
Technical Support
On-Line Manuals
Assembler Reference
Conventions and feedback
Assembler command line options
ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo--instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
NOP
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMULL, UMLAL, SMULL, and SMLAL
UMAAL
UND pseudo-instruction
USAD8 and USADA8
VFP Programming
Directives Reference
Assembler Reference
SEV, WFE, WFI, and YIELD
| |||
| Home > ARM and Thumb Instructions > SEV, WFE, WFI, and YIELD | |||
Set Event, Wait For Event, Wait for Interrupt, and Yield.
SyntaxThese are hint instructions. It is optional whether they are
implemented or not. If any one of them is not implemented, it executes
as a NOP. The assembler produces a diagnostic message
if the instruction executes as a NOP on the target.
SEV, WFE, WFI, and YIELD execute
as NOP instructions in ARMv6T2.
SEV causes an event to be signaled to all cores
within a multiprocessor system. If SEV is implemented, WFE must
also be implemented.
If the Event Register is not set, WFE suspends
execution until one of the following events occurs:
an IRQ interrupt, unless masked by the CPSR I-bit
an FIQ interrupt, unless masked by the CPSR F-bit
an Imprecise Data abort, unless masked by the CPSR A-bit
a Debug Entry request, if Debug is enabled
an Event signaled by another processor using the
SEVinstruction.
If the Event Register is set, WFE clears it and
returns immediately.
If WFE is implemented, SEV must
also be implemented.
WFI suspends execution until one of the following
events occurs:
an IRQ interrupt, regardless of the CPSR I-bit
an FIQ interrupt, regardless of the CPSR F-bit
an Imprecise Data abort, unless masked by the CPSR A-bit
a Debug Entry request, regardless of whether Debug is enabled.
These ARM instructions are available in ARMv6K and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
These 16-bit Thumb instructions are available in ARMv6T2 and above.
- Reference
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
 PDF version | |
| Home > ARM and Thumb Instructions > SEV, WFE, WFI, and YIELD |
ProductsDevelopment Tools |
Hardware & Collateral |
Downloads |
Support |
Buy |
|
 |
|||
