|
|||
| Products Download Events Support Videos | |||
Technical Support
On-Line Manuals
Assembler Reference
Conventions and feedback
Assembler command line options
ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo--instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
NOP
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMULL, UMLAL, SMULL, and SMLAL
UMAAL
UND pseudo-instruction
USAD8 and USADA8
VFP Programming
Directives Reference
Assembler Reference
MRC, MRC2, MRRC and MRRC2
| |||
| Home > ARM and Thumb Instructions > MRC, MRC2, MRRC and MRRC2 | |||
Move to ARM Register or Registers from Coprocessor.
Depending on the coprocessor, you might be able to specify various operations in addition.
Syntax{op1cond}coproc, #opcode1,Rt,CRn,CRm{, #opcode2}
{op2cond}coproc, #opcode3,Rt,Rt2,CRm
where:
op1is either
MRCorMRC2.op2is either
MRRCorMRRC2.condis an optional condition code. In ARM code,
condMRC2orMRRC2.coprocis the name of the coprocessor the instruction is for. The standard name is
p, wherennopcode1is a 3-bit coprocessor-specific opcode.
opcode2is an optional 3-bit coprocessor-specific opcode.
opcode3is a 4-bit coprocessor-specific opcode.
Rt,Rt2are ARM destination registers.
RandtRmust not be PC.t2In
MRCandMRC2,RtAPSR_nzcv. This means that the coprocessor executes an instruction that changes the value of the condition code flags in the APSR.CRn,CRmare coprocessor registers.
The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.
The MRC ARM instruction is available in all versions
of the ARM architecture.
The MRC2 ARM instruction is available in ARMv5T
and above.
The MRRC ARM instruction is available in ARMv6
and above, and E variants of ARMv5T.
The MRRC2 ARM instruction is available in ARMv6
and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There are no 16-bit Thumb versions of these instructions.
- Reference
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
 PDF version | |
| Home > ARM and Thumb Instructions > MRC, MRC2, MRRC and MRRC2 |
ProductsDevelopment Tools |
Hardware & Collateral |
Downloads |
Support |
Buy |
|
 |
|||
