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SMMUL, SMMLA, and SMMLS
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| Home > ARM and Thumb Instructions > SMMUL, SMMLA, and SMMLS | |||
Signed Most significant word Multiply, Signed Most significant word Multiply with Accumulation, and Signed Most significant word Multiply with Subtraction. These instructions have 32-bit operands and produce only the most significant 32-bits of the result.
SyntaxSMMUL{R}{cond} {Rd},Rn,Rm
SMMLA{R}{cond}Rd,Rn,Rm,Ra
SMMLS{R}{cond}Rd,Rn,Rm,Ra
where:
Ris an optional parameter. If
Ris present, the result is rounded, otherwise it is truncated.condis an optional condition code.
Rdis the destination register.
Rn, Rmare the registers holding the operands.
Rais a register holding the value to be added or subtracted from.
SMMUL multiplies the values from RnRmRd
SMMLA multiplies the values from RnRmRaRd
SMMLS multiplies the values from RnRmRaRd
If the optional R parameter is specified, 0x80000000 is
added before extracting the most significant 32 bits. This has the
effect of rounding the result.
You cannot use PC for any register.
You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
These ARM instructions are available in ARMv6 and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.
There are no 16-bit Thumb versions of these instructions.
- Reference
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
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