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SMLALD and SMLSLD
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| Home > ARM and Thumb Instructions > SMLALD and SMLSLD | |||
Dual 16-bit Signed Multiply with Addition or Subtraction of products and 64-bit Accumulation.
Syntax{X}{opcond}RdLo,RdHi,Rn,Rm
where:
opis one of:
SMLALDDual multiply, accumulate sum of products.
SMLSLDDual multiply, accumulate difference of products.
Xis an optional parameter. If
Xis present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.condis an optional condition code.
RdLo,RdHiare the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand.
RdHiRdLoRn, Rmare the registers holding the operands.
SMLALD multiplies the bottom halfword of RnRmRnRmRdLoRdHiRdLo, RdHi
SMLSLD multiplies the bottom halfword of RnRmRnRmRdLo, RdHiRdLo, RdHi
You cannot use PC for any register.
You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
These ARM instructions are available in ARMv6 and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.
There are no 16-bit Thumb versions of these instructions.
- Reference
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
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