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ARM and Thumb Instructions
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General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo--instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
NOP
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMULL, UMLAL, SMULL, and SMLAL
UMAAL
UND pseudo-instruction
USAD8 and USADA8
VFP Programming
Directives Reference
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Home / Assembler Reference
Shift operations
Register shift operations move the bits in a register left
or right by a specified number of bits, the shift length.
Register shift can be performed: directly
by the instructions ASR, LSR, LSL, ROR,
and RRX, and the result is written to a destination
register during the calculation of Operand2 by
the instructions that specify the second operand as a register with
shift. The result is used by the instruction.
The permitted shift lengths depend on the shift type and the
instruction, see the individual instruction description or the flexible
second operand description. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the
specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag.
In these descriptions, Rm is
the register containing the value to be shifted, and n is
the shift length. ASR
Arithmetic shift right by n bits
moves the left-hand 32-n bits
of the register Rm,
to the right by n places,
into the right-hand 32-n bits
of the result. And it copies the original bit[31] of the register into
the left-hand n bits
of the result. See Figure 1. You can use the ASR #n operation
to divide the value in the register Rm by
2n, with the
result being rounded towards negative-infinity. When the instruction is ASRS or when ASR
#n is used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST,
the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm. NoteIf n is
32 or more, then all the bits in the result are set to the value
of bit[31] of Rm. If n is
32 or more and the carry flag is updated, it is updated to the value
of bit[31] of Rm.
LSR
Logical shift right by n bits
moves the left-hand 32-n bits
of the register Rm,
to the right by n places,
into the right-hand 32-n bits
of the result. And it sets the left-hand n bits
of the result to 0. See Figure 2. You can use the LSR #n operation
to divide the value in the register Rm by
2n, if the
value is regarded as an unsigned integer. When the instruction is LSRS or when LSR
#n is used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST,
the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm. NoteIf n is
32 or more, then all the bits in the result are cleared to 0. If n is
33 or more and the carry flag is updated, it is updated to 0.
LSL
Logical shift left by n bits
moves the right-hand 32-n bits
of the register Rm,
to the left by n places, into
the left-hand 32-n bits
of the result. And it sets the right-hand n bits
of the result to 0. See Figure 3. You can use he LSL #n operation
to multiply the value in the register Rm by
2n, if the
value is regarded as an unsigned integer or a two’s complement signed
integer. Overflow can occur without warning. When the instruction is LSLS or when LSL
#n, with non-zero n,
is used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST,
the carry flag is updated to the last bit shifted out, bit[32-n],
of the register Rm.
These instructions do not affect the carry flag when used with LSL
#0. NoteIf n is
32 or more, then all the bits in the result are cleared to 0. If n is
33 or more and the carry flag is updated, it is updated to 0.
ROR
Rotate right by n bits
moves the left-hand 32-n bits
of the register Rm,
to the right by n places,
into the right-hand 32-n bits
of the result. And it moves the right-hand n bits
of the register into the left-hand n bits
of the result. See Figure 4. When the instruction is RORS or when ROR
#n is used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST,
the carry flag is updated to the last bit rotation, bit[n-1], of
the register Rm. NoteIf n is
32, then the value of the result is same as the value in Rm,
and if the carry flag is updated, it is updated to bit[31] of Rm. ROR with shift length, n,
more than 32 is the same as ROR with shift length n-32.
RRX
Rotate right with extend moves the bits of the register Rm to
the right by one bit. And it copies the carry flag into bit[31]
of the result. See Figure 5. When the instruction is RRXS or when RRX is
used in Operand2 with
the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST,
the carry flag is updated to bit[0] of the register Rm. See also
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