op{S}{cond} Rd, Rn, Operand2

where:

The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2.

The BIC (Bit Clear) instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

The ORN Thumb instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

In certain circumstances, the assembler can substitute BIC for AND, AND for BIC, ORN for ORR, or ORR for ORN. Be aware of this when reading disassembly listings.

You cannot use PC (R15) for Rd or any operand in any of these instructions.

You can use PC and SP in these ARM instructions but they are deprecated in ARMv6T2 and above.

If you use PC as Rn, the value used is the address of the instruction plus 8.

If you use PC as Rd:

You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.

If S is specified, these instructions:

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

In the first three cases, it does not matter if you specify OPS Rd, Rm, Rd. The instruction is the same.

    AND     r9,r2,#0xFF00
    ORREQ   r2,r0,r5
    EORS    r0,r0,r3,ROR r6

    ANDS    r9, r8, #0x19
    EORS    r7, r11, #0x18181818 
    BIC     r0, r1, #0xab

    ORN     r7, r11, lr, ROR #4

    ORNS    r7, r11, lr, ASR #32

    EORS    r0,pc,r3,ROR r6     ; PC not permitted with register
                                ; controlled shift