ADD, SUB, RSB, ADC, SBC, and RSC

op{S}{cond} {Rd}, Rn, Operand2

op{cond} {Rd}, Rn, #imm12               ; 32-bit Thumb ADD and SUB only

where:

The ADD instruction adds the values in Rn and Operand2 or imm12.

The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.

The RSB (Reverse Subtract) instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2.

You can use ADC, SBC, and RSC to synthesize multiword arithmetic.

The ADC (Add with Carry) instruction adds the values in Rn and Operand2, together with the carry flag.

The SBC (Subtract with Carry) instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one.

The RSC (Reverse Subtract with Carry) instruction subtracts the value in Rn from the value of Operand2. If the carry flag is clear, the result is reduced by one.

In certain circumstances, the assembler can substitute one instruction for another. Be aware of this when reading disassembly listings.

In most of these instructions, you cannot use PC (R15) for Rd, or any operand.

The exceptions are:

In most of these instructions, you cannot use SP (R13) for Rd, or any operand. Except that:

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

With the exception of ADD and SUB, use of PC for any operand, in instructions without register-controlled shift, is deprecated.

In SUB instructions without register-controlled shift, use of PC is deprecated except for the following cases:

In ADD instructions without register-controlled shift, use of PC is deprecated except for the following cases:

If you use PC (R15) as Rn or Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

You can use SP for Rn in ADD and SUB instructions, however, ADDS PC, SP, #Constant and SUBS PC, SP, #Constant are deprecated.

You can use SP in ADD (register) and SUB (register) if Rn is SP and shift is omitted or LSL #1, LSL #2, or LSL #3.

Other uses of SP in these ARM instructions are deprecated.

If S is specified, these instructions update the N, Z, C and V flags according to the result.

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

    ADD     r2, r1, r3
    SUBS    r8, r6, #240        ; sets the flags on the result
    RSB     r4, r4, #1280       ; subtracts contents of R4 from 1280
    ADCHI   r11, r0, r3         ; only executed if C flag set and Z
                                ; flag clear
    RSCSLE  r0,r5,r0,LSL r4     ; conditional, flags set

    RSCSLE  r0,pc,r0,LSL r4    ; PC not permitted with register
                                ; controlled shift

These two instructions add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

    ADDS    r4, r0, r2    ; adding the least significant words
    ADC     r5, r1, r3    ; adding the most significant words

These instructions subtract one 96-bit integer from another:

    SUBS    r3, r6, r9
    SBCS    r4, r7, r10
    SBC     r5, r8, r11

For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid:

    SUBS    r6, r6, r9
    SBCS    r9, r2, r1
    SBC     r2, r8, r11