VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS

ARM Compiler toolchain v5.02 for µVision Assembler Reference

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VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS

Floating-point multiply and multiply accumulate, with optional negation.

These instructions can be scalar, vector, or mixed.

Syntax

V{N}MUL{cond}.F32 {Sd,} Sn, Sm

V{N}MUL{cond}.F64 {Dd,} Dn, Dm

V{N}MLA{cond}.F32 Sd, Sn, Sm

V{N}MLA{cond}.F64 Dd, Dn, Dm

V{N}MLS{cond}.F32 Sd, Sn, Sm

V{N}MLS{cond}.F64 Dd, Dn, Dm

where:

N: negates the final result.
cond: is an optional condition code.
Sd, Sn, Sm: are the single-precision registers for the result and operands.
Dd, Dn, Dm: are the double-precision registers for the result and operands.

Usage

The VMUL operation multiplies the values in the operand registers and places the result in the destination register.

The VMLA operation multiplies the values in the operand registers, adds the value in the destination register, and places the final result in the destination register.

The VMLS operation multiplies the values in the operand registers, subtracts the result from the value in the destination register, and places the final result in the destination register.

In each case, the final result is negated if the N option is used.

Floating-point exceptions

These instructions can produce Invalid Operation, Overflow, Underflow, Inexact, or Input Denormal exceptions.

VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS