MOV{S}{cond} Rd, Operand2

MOV{cond} Rd, #imm16

MVN{S}{cond} Rd, Operand2

where:

The MOV instruction copies the value of Operand2 into Rd.

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings.

You cannot use PC (R15) for Rd, or in Operand2, in 32-bit Thumb MOV or MVN instructions. With the following exceptions, you cannot use SP (R13) for Rd, or in Operand2:

You can use PC or SP in 16-bit Thumb MOV{cond} Rd, Rm instructions but these instructions in which both Rd and Rm are SP or PC are deprecated in ARMv6T2 and above.

You cannot use PC or SP in any other MOV{S} or MVN{S} 16-bit Thumb instructions.

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

In instructions without register-controlled shift, use of PC is deprecated except the following cases:

You can use SP for Rd or Rm. But these are deprecated except the following cases:

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

If S is specified, these instructions:

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

The #imm16 form of the ARM instruction is available in ARMv6T2 and above. The other forms of the ARM instruction are available in all versions of the ARM architecture.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

    MVNNE   r11, #0xF000000B ; ARM only. This immediate value is not
                             ; available in T2.

    MVN     pc,r3,ASR r0     ; PC not permitted with register-controlled shift