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Conventions and feedback Assembler command line options ARM and Thumb Instructions Instruction summary Instruction width specifiers Memory access instructions General data processing instructions Flexible second operand (Operand2) Operand2 as a constant Operand2 as a register with optional shift Shift operations Multiply instructions Saturating instructions Parallel instructions Parallel add and subtract Packing and unpacking instructions Branch and control instructions Coprocessor instructions Miscellaneous instructions ThumbEE instructions Pseudo-instructions Condition codes ADD, SUB, RSB, ADC, SBC, and RSC ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND, ORR, EOR, BIC, and ORN ASR, LSL, LSR, ROR, and RRX B, BL, BX, BLX, and BXJ BFC and BFI BKPT CBZ and CBNZ CDP and CDP2 CHKA CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB, DSB, and ISB ENTERX and LEAVEX ERET HB, HBL, HBLP, and HBP IT LDC, LDC2, STC, and STC2 LDM and STM LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR, unprivileged LDR (PC-relative) LDR (register-relative) LDR pseudo-instruction LDREX and STREX MAR and MRA MCR, MCR2, MCRR, and MCRR2 MIA, MIAPH, and MIAxy MOV and MVN MOV32 pseudo--instruction MOVT MRC, MRC2, MRRC and MRRC2 MRS (system coprocessor register to ARM register) MRS (PSR to general-purpose register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL, MLA, and MLS NEG pseudo-instruction PKHBT and PKHTB PLD, PLDW, and PLI PUSH and POP QADD, QSUB, QDADD, and QDSUB REV, REV16, REVSH, and RBIT RFE SBFX and UBFX SDIV and UDIV SEL SETEND SEV, WFE, WFI, and YIELD SMC NOP SMLAD and SMLSD SMLALxy SMLALD and SMLSLD SMMUL, SMMLA, and SMMLS SMUAD{X} and SMUSD{X} SMULxy and SMLAxy SMULWy and SMLAWy SRS SSAT and USAT SSAT16 and USAT16 SUBS pc, lr SVC SWP and SWPB SXT, SXTA, UXT, and UXTA SYS TBB and TBH TST and TEQ UMULL, UMLAL, SMULL, and SMLAL UMAAL UND pseudo-instruction USAD8 and USADA8 VFP Programming Directives Reference

Assembler Reference

MAR and MRA

ARM Compiler toolchain v5.02 for µVision Assembler Reference
Home > ARM and Thumb Instructions > MAR and MRA

MAR and MRA

Transfer between two general-purpose registers and a 40-bit internal accumulator.

Show/hideSyntax

MAR{cond} Acc, RdLo, RdHi

MRA{cond} RdLo, RdHi, Acc

where:

cond

is an optional condition code.

Acc

is the internal accumulator. The standard name is accx,where x is an integer in the range 0 to n. The value of n depends on the processor. It is 0 for current processors.

RdLo, RdHi

are general-purpose registers. RdLo and RdHi must not be the PC, and for MRA they must be different registers.

Show/hideUsage

The MAR instruction copies the contents of RdLo to bits[31:0] of Acc, and the least significant byte of RdHi to bits[39:32] of Acc.

The MRA instruction:

  • copies bits[31:0] of Acc to RdLo

  • copies bits[39:32] of Acc to RdHi bits[7:0]

  • sign extends the value by copying bit[39] of Acc to bits[31:8] of RdHi.

Show/hideArchitectures

These ARM coprocessor 0 instructions are only available in XScale processors.

There are no Thumb versions of these instructions.

Show/hideExamples

    MAR     acc0, r0, r1
    MRA     r4, r5, acc0
    MARNE   acc0, r9, r2
    MRAGT   r4, r8, acc0

Show/hideSee also

Reference
Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
Non-ConfidentialID062912
PDF file icon  PDF version
Home > ARM and Thumb Instructions > MAR and MRA

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