SMUL<x><y>{cond} {Rd}, Rn, Rm

SMLA<x><y>{cond} Rd, Rn, Rm, Ra

where:

SMULxy multiplies the 16-bit signed integers from the selected halves of Rn and Rm, and places the 32-bit result in Rd.

SMLAxy multiplies the 16-bit signed integers from the selected halves of Rn and Rm, adds the 32-bit result to the 32-bit value in Ra, and places the result in Rd.

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

These instructions do not affect the N, Z, C, or V flags.

If overflow occurs in the accumulation, SMLAxy sets the Q flag. To read the state of the Q flag, use an MRS instruction.

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5T.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

    SMULTBEQ    r8, r7, r9
    SMLABBNE    r0, r2, r1, r10
    SMLABT      r0, r0, r3, r5