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Assembler Reference

Conventions and feedback Assembler command line options ARM and Thumb Instructions Instruction summary Instruction width specifiers Memory access instructions General data processing instructions Flexible second operand (Operand2) Operand2 as a constant Operand2 as a register with optional shift Shift operations Multiply instructions Saturating instructions Parallel instructions Parallel add and subtract Packing and unpacking instructions Branch and control instructions Coprocessor instructions Miscellaneous instructions ThumbEE instructions Pseudo-instructions Condition codes ADD, SUB, RSB, ADC, SBC, and RSC ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND, ORR, EOR, BIC, and ORN ASR, LSL, LSR, ROR, and RRX B, BL, BX, BLX, and BXJ BFC and BFI BKPT CBZ and CBNZ CDP and CDP2 CHKA CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB, DSB, and ISB ENTERX and LEAVEX ERET HB, HBL, HBLP, and HBP IT LDC, LDC2, STC, and STC2 LDM and STM LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR, unprivileged LDR (PC-relative) LDR (register-relative) LDR pseudo-instruction LDREX and STREX MAR and MRA MCR, MCR2, MCRR, and MCRR2 MIA, MIAPH, and MIAxy MOV and MVN MOV32 pseudo--instruction MOVT MRC, MRC2, MRRC and MRRC2 MRS (system coprocessor register to ARM register) MRS (PSR to general-purpose register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL, MLA, and MLS NEG pseudo-instruction PKHBT and PKHTB PLD, PLDW, and PLI PUSH and POP QADD, QSUB, QDADD, and QDSUB REV, REV16, REVSH, and RBIT RFE SBFX and UBFX SDIV and UDIV SEL SETEND SEV, WFE, WFI, and YIELD SMC NOP SMLAD and SMLSD SMLALxy SMLALD and SMLSLD SMMUL, SMMLA, and SMMLS SMUAD{X} and SMUSD{X} SMULxy and SMLAxy SMULWy and SMLAWy SRS SSAT and USAT SSAT16 and USAT16 SUBS pc, lr SVC SWP and SWPB SXT, SXTA, UXT, and UXTA SYS TBB and TBH TST and TEQ UMULL, UMLAL, SMULL, and SMLAL UMAAL UND pseudo-instruction USAD8 and USADA8 VFP Programming Directives Reference

Assembler Reference

SWP and SWPB

SWP and SWPB

Swap data between registers and memory.

Show/hideSyntax

SWP{B}{cond} Rt, Rt2, [Rn]

where:

cond

is an optional condition code.

B

is an optional suffix. If B is present, a byte is swapped. Otherwise, a 32-bit word is swapped.

Rt

is the destination register. Rt must not be PC.

Rt2

is the source register. Rt2 can be the same register as Rt. Rt2 must not be PC.

Rn

contains the address in memory. Rn must be a different register from both Rt and Rt2. Rn must not be PC.

Show/hideUsage

You can use SWP and SWPB to implement semaphores:

  • Data from memory is loaded into Rt.

  • The contents of Rt2 is saved to memory.

  • If Rt2 is the same register as Rt, the contents of the register is swapped with the contents of the memory location.

Show/hideNote

The use of SWP and SWPB is deprecated in ARMv6 and above. You can use LDREX and STREX instructions to implement more sophisticated semaphores in ARMv6 and above.

Show/hideArchitectures

These ARM instructions are available in all versions of the ARM architecture.

There are no Thumb SWP or SWPB instructions.

Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
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