|
|||
| Products Download Events Support Videos | |||
Technical Support
On-Line Manuals
Assembler Reference
Conventions and feedback
Assembler command line options
ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo--instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
NOP
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMULL, UMLAL, SMULL, and SMLAL
UMAAL
UND pseudo-instruction
USAD8 and USADA8
VFP Programming
Directives Reference
Assembler Reference
ADRL pseudo-instruction
| |||
| Home > ARM and Thumb Instructions > ADRL pseudo-instruction | |||
Load a PC-relative or register-relative address into a register.
It is similar to the ADR instruction. ADRL can
load a wider range of addresses than ADR because it
generates two data processing instructions.
Note
When assembling Thumb instructions, ADRL is only
available in ARMv6T2 and later.
SyntaxADRL{cond}Rd,label
where:
condis an optional condition code.
Rdis the register to load.
labelis a PC-relative or register-relative expression.
ADRL always assembles to two 32-bit instructions.
Even if the address can be reached in a single instruction, a second,
redundant instruction is produced.
If the assembler cannot construct the address in two instructions,
it generates an error message and the assembly fails. You can use
the LDR pseudo-instruction for loading a wider range
of addresses.
ADRL produces position-independent code, because
the address is PC-relative or register-relative.
If labelADRL pseudo-instruction.
If you use ADRL to generate a target for a BX or BLX instruction,
it is your responsibility to set the Thumb bit (bit 0) of the address
if the target contains Thumb instructions.
The available range depends on the instruction set in use:
- ARM
The range of the instruction is any value that can be generated by two
ADDor twoSUBinstructions. That is, any value that can be produced by the addition of two values, each of which is 8 bits rotated right by any even number of bits within a 32-bit word. See Operand2 as a constant for more information.- 32-bit Thumb
±1MB bytes to a byte, halfword, or word-aligned address.
- 16-bit Thumb
ADRLis not available.
The given range is relative to a point four bytes (in Thumb code) or two words (in ARM code) after the address of the current instruction.
- Concepts
Using the Assembler:
- Reference
- Other information
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
 PDF version | |
| Home > ARM and Thumb Instructions > ADRL pseudo-instruction |
ProductsDevelopment Tools |
Hardware & Collateral |
Downloads |
Support |
Buy |
|
 |
|||
