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Assembler Reference
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ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo--instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
NOP
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMULL, UMLAL, SMULL, and SMLAL
UMAAL
UND pseudo-instruction
USAD8 and USADA8
VFP Programming
Directives Reference
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Assembler Reference
PUSH and POP
Push registers onto, and pop registers off a full descending
stack. Syntax
PUSH{cond} reglist
POP{cond} reglist
where: condis an optional condition code. reglistis a non-empty list of registers, enclosed in braces.It
can contain register ranges. It must be comma separated if it contains
more than one register or register range.
Usage
PUSH is a synonym for STMDB sp!, reglist and POP is
a synonym for LDMIA sp! reglist. PUSH and POP are
the preferred mnemonics in these cases.
NoteLDM and LDMFD are synonyms of LDMIA. STMFD is
a synonym of STMDB.
Registers are stored on the stack in numerical order, with
the lowest numbered register at the lowest address. POP, with reglist including the
PC
This instruction causes a branch to the address popped off
the stack into the PC. This is usually a return from a subroutine,
where the LR was pushed onto the stack at the start of the subroutine. In ARMv5T and above: bits[1:0] must
not be 0b10 if bit[0] is 1, execution continues in Thumb state if bit[0] is 0, execution continues in ARM state.
In ARMv4, bits[1:0] of the address loaded must be 0b00. Thumb instructions
A subset of these instructions are available in the Thumb
instruction set. The following restrictions apply to the 16-bit instructions: For PUSH, reglist can
only include the Lo registers and the LR For POP, reglist can
only include the Lo registers and the PC.
The following restrictions apply to the 32-bit instructions: reglist must
not include the SP
For PUSH, reglist must
not include the PC For POP, reglist can
include either the LR or the PC, but not both.
Restrictions on reglist in ARM instructions
ARM PUSH instructions can have SP and PC in the reglist but
these instructions that include SP or PC in the reglist are
deprecated in ARMv6T2 and above. ARM POP instructions cannot have SP but can have PC in the reglist.
These instructions that include both PC and LR in the reglist are
deprecated in ARMv6T2 and above. Examples
PUSH {r0,r4-r7}
PUSH {r2,lr}
POP {r0,r10,pc} ; no 16-bit version available
See also
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