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Assembler Reference

Conventions and feedback Assembler command line options ARM and Thumb Instructions Instruction summary Instruction width specifiers Memory access instructions General data processing instructions Flexible second operand (Operand2) Operand2 as a constant Operand2 as a register with optional shift Shift operations Multiply instructions Saturating instructions Parallel instructions Parallel add and subtract Packing and unpacking instructions Branch and control instructions Coprocessor instructions Miscellaneous instructions ThumbEE instructions Pseudo-instructions Condition codes ADD, SUB, RSB, ADC, SBC, and RSC ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND, ORR, EOR, BIC, and ORN ASR, LSL, LSR, ROR, and RRX B, BL, BX, BLX, and BXJ BFC and BFI BKPT CBZ and CBNZ CDP and CDP2 CHKA CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB, DSB, and ISB ENTERX and LEAVEX ERET HB, HBL, HBLP, and HBP IT LDC, LDC2, STC, and STC2 LDM and STM LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR, unprivileged LDR (PC-relative) LDR (register-relative) LDR pseudo-instruction LDREX and STREX MAR and MRA MCR, MCR2, MCRR, and MCRR2 MIA, MIAPH, and MIAxy MOV and MVN MOV32 pseudo--instruction MOVT MRC, MRC2, MRRC and MRRC2 MRS (system coprocessor register to ARM register) MRS (PSR to general-purpose register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL, MLA, and MLS NEG pseudo-instruction PKHBT and PKHTB PLD, PLDW, and PLI PUSH and POP QADD, QSUB, QDADD, and QDSUB REV, REV16, REVSH, and RBIT RFE SBFX and UBFX SDIV and UDIV SEL SETEND SEV, WFE, WFI, and YIELD SMC NOP SMLAD and SMLSD SMLALxy SMLALD and SMLSLD SMMUL, SMMLA, and SMMLS SMUAD{X} and SMUSD{X} SMULxy and SMLAxy SMULWy and SMLAWy SRS SSAT and USAT SSAT16 and USAT16 SUBS pc, lr SVC SWP and SWPB SXT, SXTA, UXT, and UXTA SYS TBB and TBH TST and TEQ UMULL, UMLAL, SMULL, and SMLAL UMAAL UND pseudo-instruction USAD8 and USADA8 VFP Programming Directives Reference

Assembler Reference

ADR (PC-relative)

ADR (PC-relative)

ADR generates a PC-relative address in the destination register, for a label in the current area.

Show/hideSyntax

ADR{cond}{.W} Rd,label

where:

cond

is an optional condition code.

.W

is an optional instruction width specifier.

Rd

is the destination register to load.

label

is a PC-relative expression.

label must be within a limited distance of the current instruction.

Show/hideUsage

ADR produces position-independent code, because the assembler generates an instruction that adds or subtracts a value to the PC.

Use the ADRL pseudo-instruction to assemble a wider range of effective addresses.

label must evaluate to an address in the same assembler area as the ADR instruction.

If you use ADR to generate a target for a BX or BLX instruction, it is your responsibility to set the Thumb bit (bit 0) of the address if the target contains Thumb instructions.

Show/hideOffset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Table 6 shows the possible offsets between the label and the current instruction.

Table 6. PC-relative offsets

InstructionOffset rangeArchitectures[a]
ARM ADRSee Operand2 as a constantAll
32-bit Thumb ADR+/- 4095T2
16-bit Thumb ADR [b]0-1020 [c]T

[a] Entries in the Architectures column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

T2

The ARMv6T2 and above architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

[b] Rd must be in the range R0-R7.

[c] Must be a multiple of 4.


Show/hideADR in 32-bit Thumb

You can use the .W width specifier to force ADR to generate a 32-bit instruction in Thumb code. ADR with .W always generates a 32-bit instruction, even if the address can be generated in a 16-bit instruction.

For forward references, ADR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for an address that could be generated in a 32-bit Thumb ADD instruction.

Show/hideRestrictions

In Thumb code, Rd cannot be PC or SP.

In ARM code, Rd can be PC or SP but use of SP is deprecated in ARMv6T2 and above.

Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
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