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MRS (system coprocessor register to ARM register)
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MSR (general-purpose register to PSR)
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MSR (general-purpose register to PSR)
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| Home > ARM and Thumb Instructions > MSR (general-purpose register to PSR) | |||
Load an immediate value, or the contents of a general-purpose register, into specified fields of a Program Status Register (PSR).
SyntaxMSR{cond} APSR_flags,Rm
where:
condis an optional condition code.
flagsspecifies the APSR flags to be moved.
flagsnzcvqALU flags field mask, PSR[31:27] (User mode)
gSIMD GE flags field mask, PSR[19:16] (User mode).
Rmis the source register.
Rmust not be PC.m
You can also use the following syntax on architectures other than ARMv7-M and ARMv6-M.
MSR{cond} APSR_flags, #constant
MSR{cond}psr_fields, #constant
MSR{cond}psr_fields,Rm
where:
condis an optional condition code.
flagsspecifies the APSR flags to be moved.
flagsnzcvqALU flags field mask, PSR[31:27] (User mode)
gSIMD GE flags field mask, PSR[19:16] (User mode).
constantis an expression evaluating to a numeric value. The value must correspond to an 8-bit pattern rotated by an even number of bits within a 32-bit word. Not available in Thumb.
Rmis the source register.
Rmust not be PC.mpsris one of:
CPSRfor use in Debug state, also deprecated synonym for APSR
SPSRon any processor, in privileged software execution only.
fieldsspecifies the SPSR or CPSR fields to be moved.
fieldsccontrol field mask byte, PSR[7:0] (privileged software execution)
xextension field mask byte, PSR[15:8] (privileged software execution)
sstatus field mask byte, PSR[23:16] (privileged software execution)
fflags field mask byte, PSR[31:24] (privileged software execution).
You can also use the following syntax on ARMv7-M and ARMv6-M.
MSR{cond}psr,Rm
where:
condis an optional condition code.
Rmis the source register.
Rmust not be PC.mpsrcan be any of:
APSR,IPSR,EPSR,IEPSR,IAPSR,EAPSR,XPSR,MSP,PSP,PRIMASK,BASEPRI,BASEPRI_MAX,FAULTMASK, orCONTROL.
In User mode:
Use APSR to access condition flags, Q, or GE bits.
Writes to unallocated, privileged or execution state bits in the CPSR are ignored. This ensures that User mode programs cannot change to privileged software execution.
If you access the SPSR when in User or System mode, the result is unpredictable.
If R is PC
in ARM instructions, the result is unpredictable.
You can use SP for mR in
ARM instructions but this is deprecated in ARMv6T2 and above.m
If R is PC
or SP in Thumb instructions, the result is unpredictable.m
This instruction updates the flags explicitly if the APSR_nzcvq or CPSR_f field
is specified.
This ARM instruction is available in all versions of the ARM architecture.
This 32-bit Thumb instruction is available in ARMv6T2 and above.
There is no 16-bit Thumb version of this instruction.
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
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