Assembler User GuidePreface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Architecture support for VFP Half-precision extension for VFP Fused Multiply-Add extension for VFP Extension register bank mapping in VFP VFP views of the extension register bank Load values to VFP registers Conditional execution of VFP instructions Floating-point exceptions in VFP VFP data types Extended notation extension for VFP VFP system registers Flush-to-zero mode When to use flush-to-zero mode in VFP The effects of using flush-to-zero mode in VFP VFP operations not affected by flush-to-zero mode VFP vector mode Vectors in the VFP extension register bank VFP vector wrap-around VFP vector stride Restriction on vector length Control of scalar, vector, and mixed operations Overview of VFP directives and vector notation Pre-UAL VFP syntax and mnemonics Vector notation VFPASSERT SCALAR VFPASSERT VECTOR Assembler Command-line Options ARM and Thumb Instructions VFP Instructions Directives Reference Via File Syntax
Extension register bank mapping in VFP
8.4 Extension register bank mapping in VFP
The VFP extension register bank is a collection of registers that can be accessed as either 32-bit or 64-bit registers.
The following figure shows the views of the VFP extension register bank, and the overlap between the different size registers. For example, the 64-bit register
Figure 8-1 VFP extension register bank
The figure applies to a VFP implementation with 32 double precision registers. The following versions of VFP use 16 double precision registers,
The aliased views enable half-precision, single-precision, and double-precision values to coexist in different non-overlapped registers at the same time.
You can also use the same overlapped registers to store half-precision, single-precision, and double-precision values at different times.
Do not attempt to use overlapped 32-bit and 64-bit registers at the same time because it creates meaningless results.
The mapping between the registers is as follows:
For example, you can access the least significant half of the elements of a vector in
of your data.