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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax

ADR (PC-relative)

10.11 ADR (PC-relative)

Generate a PC-relative address in the destination register, for a label in the current area.

Syntax

ADR{cond}{.W} Rd,label
where:
cond
is an optional condition code.
.W
is an optional instruction width specifier.
Rd
is the destination register to load.
label
is a PC-relative expression.
label must be within a limited distance of the current instruction.

Usage

ADR produces position-independent code, because the assembler generates an instruction that adds or subtracts a value to the PC.
Use the ADRL pseudo-instruction to assemble a wider range of effective addresses.
label must evaluate to an address in the same assembler area as the ADR instruction.
If you use ADR to generate a target for a BX or BLX instruction, it is your responsibility to set the Thumb bit (bit 0) of the address if the target contains Thumb instructions.

Offset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.
The following table shows the possible offsets between the label and the current instruction:

Table 10-3 PC-relative offsets

Instruction Offset range Architectures
ARM ADR Any value that can be produced by rotating an 8-bit value right by any even number of bits within a 32-bit word. All
Thumb ADR, 32-bit encoding +/– 4095 T2
Thumb ADR, 16-bit encoding a 0-1020 b T

Notes about the Architectures column

Entries in the Architectures column indicate that the instructions are available as follows:
All
All versions of the ARM architecture.
T2
The ARMv6T2 and above architectures.
T
The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

ADR in Thumb

You can use the .W width specifier to force ADR to generate a 32-bit instruction in Thumb code. ADR with .W always generates a 32-bit instruction, even if the address can be generated in a 16-bit instruction.
For forward references, ADR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for an address that could be generated in a 32-bit Thumb ADD instruction.

Restrictions

In Thumb code, Rd cannot be PC or SP.
In ARM code, Rd can be PC or SP but use of SP is deprecated in ARMv6T2 and above.
a 
Rd must be in the range R0-R7.
b 
Must be a multiple of 4.
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