ADR (PC-relative)

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ARM DUI0379H

ARM^® Compiler v5.06 for µVision^® armasm User Guide

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10.11 ADR (PC-relative)

Generate a PC-relative address in the destination register, for a label in the current area.

Syntax

ADR{cond}{.W}
              Rd,label

where:

cond: is an optional condition code.
.W: is an optional instruction width specifier.
Rd: is the destination register to load.
label: is a PC-relative expression.

label must be within a limited distance of the current instruction.

Usage

ADR produces position-independent code, because the assembler generates an instruction that adds or subtracts a value to the PC.

Use the ADRL pseudo-instruction to assemble a wider range of effective addresses.

label must evaluate to an address in the same assembler area as the ADR instruction.

If you use ADR to generate a target for a BX or BLX instruction, it is your responsibility to set the Thumb bit (bit 0) of the address if the target contains Thumb instructions.

Offset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

The following table shows the possible offsets between the label and the current instruction:

Table 10-3 PC-relative offsets

Instruction	Offset range	Architectures
ARM `ADR`	Any value that can be produced by rotating an 8-bit value right by any even number of bits within a 32-bit word.	All
Thumb `ADR`, 32-bit encoding	+/– 4095	T2
Thumb `ADR`, 16-bit encoding ^a	0-1020 ^b	T

Notes about the Architectures column

Entries in the Architectures column indicate that the instructions are available as follows:

All: All versions of the ARM architecture.
T2: The ARMv6T2 and above architectures.
T: The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

ADR in Thumb

You can use the .W width specifier to force ADR to generate a 32-bit instruction in Thumb code. ADR with .W always generates a 32-bit instruction, even if the address can be generated in a 16-bit instruction.

For forward references, ADR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for an address that could be generated in a 32-bit Thumb ADD instruction.