|
|||||||||||
Technical Support On-Line Manuals Assembler User Guide ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
USAX
10.176 USAXUnsigned parallel subtract and add halfwords with exchange. Syntax
where:
OperationThis instruction exchanges the two halfwords of the second
operand, then performs a subtraction on the two top halfwords of
the operands and an addition on the bottom two halfwords. It writes
the results into the corresponding halfwords of the destination.
The results are modulo 216. It sets the
APSR GE flags.
Register restrictionsYou cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated
in ARMv6T2 and above. You cannot use SP in Thumb instructions.
GE flagsThis instruction does not affect the N, Z, C, V, or Q flags.
It sets the GE flags in the APSR as follows:
It sets GE[1:0] to 1 to indicate that the addition overflowed, generating a carry. This is
equivalent to an
ADDS instruction setting the C condition flag to 1.It sets GE[3:2] to 1 to indicate that the subtraction gave a result greater than or equal to
zero, meaning a borrow did not occur. This is equivalent to a
SUBS
instruction setting the C condition flag to 1. You can use these flags to control a following
SEL instruction.NoteGE[1:0] are set or cleared together, and GE[3:2] are set or
cleared together.
ArchitecturesThis ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M
architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.
| ||||||||||
|
Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.