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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax

SUB

10.137 SUB

Subtract without carry.

Syntax

SUB{S}{cond} {Rd}, Rn, Operand2
SUB{cond} {Rd}, Rn, #imm12 ; Thumb, 32-bit encoding only
where:
S
is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
cond
is an optional condition code.
Rd
is the destination register.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand.
imm12
is any value in the range 0-4095.

Operation

The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
In certain circumstances, the assembler can substitute one instruction for another. Be aware of this when reading disassembly listings.

Use of PC and SP in Thumb instructions

In general, you cannot use PC (R15) for Rd, or any operand. The exception is you can use PC for Rn in 32-bit Thumb SUB instructions, with a constant Operand2 value in the range 0-4095, and no S suffix. These instructions are useful for generating PC-relative addresses. Bit[1] of the PC value reads as 0 in this case, so that the base address for the calculation is always word-aligned.
Generally, you cannot use SP (R13) for Rd, or any operand, except that you can use SP for Rn.

Use of PC and SP in ARM instructions

You cannot use PC for Rd or any operand in a SUB instruction that has a register-controlled shift.
In SUB instructions without register-controlled shift, use of PC is deprecated except for the following cases:
  • Use of PC for Rd.
  • Use of PC for Rn in the instruction SUB{cond} Rd, Rn, #Constant.
If you use PC (R15) as Rn or Rm, the value used is the address of the instruction plus 8.
If you use PC as Rd:
  • Execution branches to the address corresponding to the result.
  • If you use the S suffix, see the SUBS pc,lr instruction.
You can use SP for Rn in SUB instructions, however, SUBS PC, SP, #Constant is deprecated.
You can use SP in SUB (register) if Rn is SP and shift is omitted or LSL #1, LSL #2, or LSL #3.
Other uses of SP in ARM SUB instructions are deprecated.

Note

The deprecation of SP and PC in ARM instructions is only in ARMv6T2 and above.

Condition flags

If S is specified, the SUB instruction updates the N, Z, C and V flags according to the result.

16-bit instructions

The following forms of this instruction are available in Thumb code, and are 16-bit instructions:
SUBS Rd, Rn, Rm
Rd, Rn and Rm must all be Lo registers. This form can only be used outside an IT block.
SUB{cond} Rd, Rn, Rm
Rd, Rn and Rm must all be Lo registers. This form can only be used inside an IT block.
SUBS Rd, Rn, #imm
imm range 0-7. Rd and Rn must both be Lo registers. This form can only be used outside an IT block.
SUB{cond} Rd, Rn, #imm
imm range 0-7. Rd and Rn must both be Lo registers. This form can only be used inside an IT block.
SUBS Rd, Rd, #imm
imm range 0-255. Rd must be a Lo register. This form can only be used outside an IT block.
SUB{cond} Rd, Rd, #imm
imm range 0-255. Rd must be a Lo register. This form can only be used inside an IT block.
SUB{cond} SP, SP, #imm
imm range 0-508, word aligned.

Example

    SUBS    r8, r6, #240        ; sets the flags based on the result

Multiword arithmetic examples

These instructions subtract one 96-bit integer contained in R9, R10, and R11 from another 96-bit integer contained in R6, R7, and R8, and place the result in R3, R4, and R5:
    SUBS    r3, r6, r9
    SBCS    r4, r7, r10
    SBC     r5, r8, r11
For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid:
    SUBS    r6, r6, r9
    SBCS    r9, r2, r1
    SBC     r2, r8, r11
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