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Assembler User Guide
Preface
Overview of the Assembler
Overview of the ARM Architecture
Structure of Assembly Language Modules
Writing ARM Assembly Language
Condition Codes
Using the Assembler
Symbols, Literals, Expressions, and Operators
VFP Programming
Assembler Command-line Options
ARM and Thumb Instructions
ARM and Thumb instruction summary
Instruction width specifiers
Flexible second operand (Operand2)
Syntax of Operand2 as a constant
Syntax of Operand2 as a register with optional shi
Shift operations
Saturating instructions
Condition code suffixes
ADC
ADD
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND
ASR
B
BFC
BFI
BIC
BKPT
BL
BLX
BX
BXJ
CBZ and CBNZ
CDP and CDP2
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB
DSB
EOR
ERET
HVC
ISB
IT
LDC and LDC2
LDM
LDR (immediate offset)
LDR (PC-relative)
LDR (register offset)
LDR (register-relative)
LDR pseudo-instruction
LDR, unprivileged
LDREX
LSL
LSR
MCR and MCR2
MCRR and MCRR2
MLA
MLS
MOV
MOV32 pseudo-instruction
MOVT
MRC and MRC2
MRRC and MRRC2
MRS (PSR to general-purpose register)
MRS (system coprocessor register to ARM register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL
MVN
NEG pseudo-instruction
NOP
ORN (Thumb only)
ORR
PKHBT and PKHTB
PLD and PLI
POP
PUSH
QADD
QADD8
QADD16
QASX
QDADD
QDSUB
QSAX
QSUB
QSUB8
QSUB16
RBIT
REV
REV16
REVSH
RFE
ROR
RRX
RSB
RSC
SADD8
SADD16
SASX
SBC
SBFX
SDIV
SEL
SETEND
SEV
SHADD8
SHADD16
SHASX
SHSAX
SHSUB8
SHSUB16
SMC
SMLAxy
SMLAD
SMLAL
SMLALD
SMLALxy
SMLAWy
SMLSD
SMLSLD
SMMLA
SMMLS
SMMUL
SMUAD
SMULxy
SMULL
SMULWy
SMUSD
SRS
SSAT
SSAT16
SSAX
SSUB8
SSUB16
STC and STC2
STM
STR (immediate offset)
STR (register offset)
STR, unprivileged
STREX
SUB
SUBS pc, lr
SVC
SWP and SWPB
SXTAB
SXTAB16
SXTAH
SXTB
SXTB16
SXTH
SYS
TBB and TBH
TEQ
TST
UADD8
UADD16
UASX
UBFX
UDIV
UHADD8
UHADD16
UHASX
UHSAX
UHSUB8
UHSUB16
UMAAL
UMLAL
UMULL
UND pseudo-instruction
UQADD8
UQADD16
UQASX
UQSAX
UQSUB8
UQSUB16
USAD8
USADA8
USAT
USAT16
USAX
USUB8
USUB16
UXTAB
UXTAB16
UXTAH
UXTB
UXTB16
UXTH
WFE
WFI
YIELD
VFP Instructions
Directives Reference
Via File Syntax
SMLSLD
| Non-Confidential |  PDF version | ARM DUI0379H | ||
| ||||
| Home > ARM and Thumb Instructions > SMLSLD | ||||
10.116 SMLSLD
Dual 16-bit Signed Multiply with Subtraction of products and 64-bit accumulation.
Syntax
SMLSD{X}{condRdLoRdHiRnRmwhere:
X- is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
cond- is an optional condition code.
RdLo,RdHi- are the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand.
RdHiandRdLomust be different registers. Rn, Rm- are the registers holding the operands.
Operation
SMLSLD multiplies the bottom halfword of Rn with the bottom
halfword of Rm, and the top halfword of Rn with the
top halfword of Rm. It then subtracts the second product from the first,
adds the difference to the value in RdLo, RdHi, and
stores the result to RdLo, RdHi.Register restrictions
You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated
in ARMv6T2 and above. You cannot use SP in Thumb instructions.
Condition flags
This instruction does not change the flags.
Architectures
This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and
above. For the ARMv7-M architecture, it is only available in an
ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.
Example
SMLSLD r3, r0, r5, r1
Related reference
| Non-Confidential | PDF version | ARM DUI0379H |
| Copyright © 2007, 2008, 2011, 2012, 2014-2016 ARM. All rights reserved. |
| Home > ARM and Thumb Instructions > SMLSLD |
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