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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax

PLD and PLI

10.71 PLD and PLI

Preload Data and Preload Instruction allow the processor to signal the memory system that a data or instruction load from an address is likely in the near future.

Syntax

PLtype{cond} [Rn {, #offset}]
PLtype{cond} [Rn, ±Rm {, shift}]
PLtype{cond} label
where:
type
can be one of:
D
Data address.
I
Instruction address.
cond
is an optional condition code.

Note

cond is permitted only in Thumb code, using a preceding IT instruction. This is an unconditional instruction in ARM code and you must not use cond.
Rn
is the register on which the memory address is based.
offset
is an immediate offset. If offset is omitted, the address is the value in Rn.
Rm
is a register containing a value to be used as the offset.
shift
is an optional shift.
label
is a PC-relative expression.

Range of offsets

The offset is applied to the value in Rn before the preload takes place. The result is used as the memory address for the preload. The range of offsets permitted is:
  • –4095 to +4095 for ARM instructions.
  • –255 to +4095 for Thumb instructions, when Rn is not PC.
  • –4095 to +4095 for Thumb instructions, when Rn is PC.
The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Register or shifted register offset

In ARM code, the value in Rm is added to or subtracted from the value in Rn. In Thumb code, the value in Rm can only be added to the value in Rn. The result is used as the memory address for the preload.
The range of shifts permitted is:
  • LSL #0 to #3 for Thumb instructions.
  • Any one of the following for ARM instructions:
    • LSL #0 to #31.
    • LSR #1 to #32.
    • ASR #1 to #32.
    • ROR #1 to #31.
    • RRX.

Address alignment for preloads

No alignment checking is performed for preload instructions.

Register restrictions

Rm must not be PC. For Thumb instructions Rm must also not be SP.
Rn must not be PC for Thumb instructions of the syntax PLtype{cond} [Rn, ±Rm{, #shift}].

Architectures

ARM PLD is available in ARMv5TE and above.
The 32-bit Thumb encoding of PLD is available in ARMv6T2 and above.
PLI is available only in ARMv7 and above.
There are no 16-bit encodings of PLD or PLI in Thumb.
These are hint instructions, and their implementation is optional. If they are not implemented, they execute as NOPs.
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