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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options ARM and Thumb Instructions ARM and Thumb instruction summary Instruction width specifiers Flexible second operand (Operand2) Syntax of Operand2 as a constant Syntax of Operand2 as a register with optional shi Shift operations Saturating instructions Condition code suffixes ADC ADD ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND ASR B BFC BFI BIC BKPT BL BLX BX BXJ CBZ and CBNZ CDP and CDP2 CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB DSB EOR ERET HVC ISB IT LDC and LDC2 LDM LDR (immediate offset) LDR (PC-relative) LDR (register offset) LDR (register-relative) LDR pseudo-instruction LDR, unprivileged LDREX LSL LSR MCR and MCR2 MCRR and MCRR2 MLA MLS MOV MOV32 pseudo-instruction MOVT MRC and MRC2 MRRC and MRRC2 MRS (PSR to general-purpose register) MRS (system coprocessor register to ARM register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL MVN NEG pseudo-instruction NOP ORN (Thumb only) ORR PKHBT and PKHTB PLD and PLI POP PUSH QADD QADD8 QADD16 QASX QDADD QDSUB QSAX QSUB QSUB8 QSUB16 RBIT REV REV16 REVSH RFE ROR RRX RSB RSC SADD8 SADD16 SASX SBC SBFX SDIV SEL SETEND SEV SHADD8 SHADD16 SHASX SHSAX SHSUB8 SHSUB16 SMC SMLAxy SMLAD SMLAL SMLALD SMLALxy SMLAWy SMLSD SMLSLD SMMLA SMMLS SMMUL SMUAD SMULxy SMULL SMULWy SMUSD SRS SSAT SSAT16 SSAX SSUB8 SSUB16 STC and STC2 STM STR (immediate offset) STR (register offset) STR, unprivileged STREX SUB SUBS pc, lr SVC SWP and SWPB SXTAB SXTAB16 SXTAH SXTB SXTB16 SXTH SYS TBB and TBH TEQ TST UADD8 UADD16 UASX UBFX UDIV UHADD8 UHADD16 UHASX UHSAX UHSUB8 UHSUB16 UMAAL UMLAL UMULL UND pseudo-instruction UQADD8 UQADD16 UQASX UQSAX UQSUB8 UQSUB16 USAD8 USADA8 USAT USAT16 USAX USUB8 USUB16 UXTAB UXTAB16 UXTAH UXTB UXTB16 UXTH WFE WFI YIELD VFP Instructions Directives Reference Via File Syntax

MOV32 pseudo-instruction

10.56 MOV32 pseudo-instruction

Load a register with either a 32-bit immediate value or any address.

Syntax

MOV32{cond} Rd, expr
where:
cond
is an optional condition code.
Rd
is the register to be loaded. Rd must not be SP or PC.
expr
can be any one of the following:
symbol
A label in this or another program area.
#constant
Any 32-bit immediate value.
symbol + constant
A label plus a 32-bit immediate value.

Usage

MOV32 always generates two 32-bit instructions, a MOV, MOVT pair. This enables you to load any 32-bit immediate, or to access the whole 32-bit address space.
The main purposes of the MOV32 pseudo-instruction are:
  • To generate literal constants when an immediate value cannot be generated in a single instruction.
  • To load a PC-relative or external address into a register. The address remains valid regardless of where the linker places the ELF section containing the MOV32.

    Note

    An address loaded in this way is fixed at link time, so the code is not position-independent.
MOV32 sets the Thumb bit (bit 0) of the address if the label referenced is in Thumb code.

Architectures

This pseudo-instruction is available in ARMv6T2 and above in both ARM and Thumb.

Examples

     MOV32 r3, #0xABCDEF12  ; loads 0xABCDEF12 into R3
     MOV32 r1, Trigger+12   ; loads the address that is 12 bytes 
                            ; higher than the address Trigger into R1
Non-ConfidentialPDF file icon PDF versionARM DUI0379H
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