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Assembler User Guide

Preface Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules Writing ARM Assembly Language Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP Programming Assembler Command-line Options --16 --32 --apcs=qualifier…qualifier --arm --arm_only --bi --bigend --brief_diagnostics, --no_brief_diagnostics --checkreglist --comment_section, --no_comment_section --compatible=name --cpreproc --cpreproc_opts=option[,option,…] --cpu=list --cpu=name --debug --depend=dependfile --depend_format=string --diag_error=tag[,tag,…] --diag_remark=tag[,tag,…] --diag_style={arm|ide|gnu} --diag_suppress=tag[,tag,…] --diag_warning=tag[,tag,…] --dllexport_all --dwarf2 --dwarf3 --errors=errorfile --execstack, --no_execstack --execute_only --exceptions, --no_exceptions --exceptions_unwind, --no_exceptions_unwind --fpmode=model --fpu=list --fpu=name -g --help -idir[,dir, …] --keep --length=n --li --library_type=lib --liclinger=seconds --list=file --list= --littleend -m --maxcache=n --md --no_code_gen --no_esc --no_hide_all --no_regs --no_terse --no_warn -o filename --pd --predefine "directive" --reduce_paths, --no_reduce_paths --regnames --report-if-not-wysiwyg --show_cmdline --split_ldm --thumb --thumbx --unaligned_access, --no_unaligned_access --unsafe --untyped_local_labels --version_number --via=filename --vsn --width=n --xref ARM and Thumb Instructions VFP Instructions Directives Reference Via File Syntax


9.62 --split_ldm

Instructs the assembler to fault LDM and STM instructions with a large number of registers.


This option is deprecated.
This option faults LDM instructions if the maximum number of registers transferred exceeds:
  • Five, for LDMs that do not load the PC.
  • Four, for LDMs that load the PC.
This option faults STM instructions if the maximum number of registers transferred exceeds 5.
Avoiding large multiple register transfers can reduce interrupt latency on ARM systems that:
  • Do not have a cache or a write buffer (for example, a cacheless ARM7TDMI).
  • Use zero wait-state, 32-bit memory.
Also, avoiding large multiple register transfers:
  • Always increases code size.
  • Has no significant benefit for cached systems or processors with a write buffer.
  • Has no benefit for systems without zero wait-state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. This is typically much greater than the latency introduced by multiple register transfers.
Related reference
Non-ConfidentialPDF file icon PDF versionARM DUI0379H
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