Condition code suffixes and related flags

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ARM DUI0379H

ARM^® Compiler v5.06 for µVision^® armasm User Guide

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5.5 Condition code suffixes and related flags

Condition code suffixes define the conditions that must be met for the instruction to execute.

The following table shows the condition codes that you can use and the flag settings they depend on:

Table 5-1 Condition code suffixes and related flags

Suffix	Flags	Meaning
`EQ`	`Z` set	Equal
`NE`	`Z` clear	Not equal
`CS` or `HS`	`C` set	Higher or same (unsigned >= )
`CC` or `LO`	`C` clear	Lower (unsigned < )
`MI`	`N` set	Negative
`PL`	`N` clear	Positive or zero
`VS`	`V` set	Overflow
`VC`	`V` clear	No overflow
`HI`	`C` set and `Z` clear	Higher (unsigned >)
`LS`	`C` clear or `Z` set	Lower or same (unsigned <=)
`GE`	`N` and `V` the same	Signed >=
`LT`	`N` and `V` differ	Signed <
`GT`	`Z` clear, `N` and `V` the same	Signed >
`LE`	`Z` set, `N` and `V` differ	Signed <=
`AL`	Any	Always. This suffix is normally omitted.

The optional condition code is shown in syntax descriptions as {cond}. This condition is encoded in a preceding IT instruction. An instruction with a condition code is only executed if the condition flags in the APSR meet the specified condition.

On processors before ARMv6T2, the {cond} field is only permitted on certain branch instructions because there is no IT instruction on these processors.

The following is an example of conditional execution:

    ADD     r0, r1, r2    ; r0 = r1 + r2, don't update flags
    ADDS    r0, r1, r2    ; r0 = r1 + r2, and update flags
    ADDSCS  r0, r1, r2    ; If C flag set then r0 = r1 + r2, 
                          ; and update flags
    CMP     r0, r1        ; update flags based on r0-r1.