|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Technical Support On-Line Manuals Assembler User Guide ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Condition code suffixes and related flags
5.5 Condition code suffixes and related flagsCondition code suffixes define the conditions that must be met for the instruction to execute. The following table shows the condition codes that you can use and the flag settings they
depend on:
Table 5-1 Condition code suffixes and related flags
The optional condition code is shown in syntax descriptions as
{ . This condition is encoded in a preceding
IT instruction. An instruction with a condition code is only executed
if the condition flags in the APSR meet the specified condition.On processors before ARMv6T2, the
{ field is
only permitted on certain branch instructions because there is no IT
instruction on these processors.The following is an example of conditional execution:
ADD r0, r1, r2 ; r0 = r1 + r2, don't update flags ADDS r0, r1, r2 ; r0 = r1 + r2, and update flags ADDSCS r0, r1, r2 ; If C flag set then r0 = r1 + r2, ; and update flags CMP r0, r1 ; update flags based on r0-r1. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.