Keil Logo

Current Program Status Register

2.16 Current Program Status Register

The Current Program Status Register (CPSR) holds the same program status flags as the APSR, and some additional information.

The CPSR holds:
  • The APSR flags.
  • The processor mode.
  • The interrupt disable flags.
  • The instruction set state (ARM, Thumb, ThumbEE, or Jazelle®).
  • The endianness state (on ARMv4T and later).
  • The execution state bits for the IT block (on ARMv6T2 and later).
The execution state bits control conditional execution in the IT block.
Only the APSR flags are accessible in all modes. ARM deprecates using an MSR instruction to change the endianness bit (E) of the CPSR, in any mode. SETEND is the preferred instruction to write to the E bit.
The execution state bits for the IT block (IT[1:0]), Jazelle bit (J), and Thumb bit (T) can be accessed by MRS only in Debug state.

Note

The CPSR is not present in ARMv6-M and ARMv7-M processors.
Non-ConfidentialPDF file icon PDF versionARM DUI0379H
Copyright © 2007, 2008, 2011, 2012, 2014-2016 ARM. All rights reserved. 
  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.