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Preface Introduction Writing ARM Assembly Language Assembler Reference 
ARM and Thumb Instructions 
Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives ReferenceNOP, SEV, WFE, WFI, and YIELD
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| Home > ARM and Thumb Instructions > Miscellaneous instructions > NOP, SEV, WFE, WFI, and YIELD | |||
No Operation, Set Event, Wait For Event, Wait for Interrupt, and Yield.
NOP{cond}
SEV{cond}
WFE{cond}
WFI{cond}
YIELD{cond}
where:
condis an optional condition code (see Conditional execution).
These are hint instructions. It is optional whether they are implemented or not. If any one of them is not implemented, it behaves as a NOP.
NOP does nothing. If NOP is not implemented as a specific instruction on your target architecture, the assembler treats it as a pseudo-instruction and generates an alternative instruction that does nothing, such as MOV r0, r0 (ARM) or MOV r8, r8 (Thumb).
NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage.
You can use NOP for padding, for example to place the following instruction on a 64-bit boundary.
SEV causes an event to be signaled to all cores within a multiprocessor system. If SEV is implemented, WFE must also be implemented.
If the Event Register is not set, WFE suspends execution until one of the following events occurs:
an IRQ interrupt, unless masked by the CPSR I-bit
an FIQ interrupt, unless masked by the CPSR F-bit
an Imprecise Data abort, unless masked by the CPSR A-bit
a Debug Entry request, if Debug is enabled
an Event signaled by another processor using the
SEVinstruction.
If the Event Register is set, WFE clears it and returns immediately.
If WFE is implemented, SEV must also be implemented.
WFI suspends execution until one of the following events occurs:
an IRQ interrupt, regardless of the CPSR I-bit
an FIQ interrupt, regardless of the CPSR F-bit
an Imprecise Data abort, unless masked by the CPSR A-bit
a Debug Entry request, regardless of whether Debug is enabled.
These ARM instructions are available in ARMv6K and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
These 16-bit Thumb instructions are available in ARMv6T2 and above.
NOP is available on all other ARM and Thumb architectures as a pseudo-instruction.
SEV, WFE, WFI, and YIELD execute as NOP instructions in ARMv6T2.
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