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Preface Introduction Writing ARM Assembly Language Assembler Reference 
ARM and Thumb Instructions 
Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives ReferenceQADD, QSUB, QDADD, and QDSUB
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| Home > ARM and Thumb Instructions > Saturating instructions > QADD, QSUB, QDADD, and QDSUB | |||
Signed Add, Subtract, Double and Add, Double and Subtract, saturating the result to the signed range –231 = x = 231–1.
See also Parallel add and subtract.
op{cond} {Rd},Rm,Rn
where:
opis one of
QADD,QSUB,QDADD, orQDSUB.condis an optional condition code (see Conditional execution).
Rdis the destination register.
Rm, Rnare the registers holding the operands.
Do not use r15 for RdRmRn
The QADD instruction adds the values in RmRn
The QSUB instruction subtracts the value in RnRm
The QDADD instruction calculates SAT(. Saturation can occur on the doubling operation, on the addition, or on both. If saturation occurs on the doubling but not on the addition, the Q flag is set but the final result is unsaturated.Rm + SAT(Rn * 2))
The QDSUB instruction calculates SAT(. Saturation can occur on the doubling operation, on the subtraction, or on both. If saturation occurs on the doubling but not on the subtraction, the Q flag is set but the final result is unsaturated.Rm - SAT(Rn * 2))
Note
All values are treated as two’s complement signed integers by these instructions.
See also Parallel add and subtract for similar parallel instructions, available in ARMv6 and above only.
If saturation occurs, these instructions set the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS).
These ARM instructions are available in ARMv6 and above, and E variants of ARMv5.
These 32-bit Thumb instructions are available in ARMv6T2 and above, except the ARMv7-M profile.
There are no 16-bit Thumb versions of these instructions.
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