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Preface Introduction Writing ARM Assembly Language Assembler Reference ARM and Thumb Instructions Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives Reference

SVC

RealView Compilation Tools for µVision Assembler GuideVersion 4.0
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4.10.2. SVC

SuperVisor Call.

Syntax

SVC{cond} #immed

where:

cond

is an optional condition code (see Conditional execution).

immed

is an expression evaluating to an integer in the range:

  • 0 to 224–1 (a 24-bit value) in an ARM instruction

  • 0-255 (an 8-bit value) in a 16-bit Thumb instruction.

Usage

The SVC instruction causes an exception. This means that the processor mode changes to Supervisor, the CPSR is saved to the Supervisor mode SPSR, and execution branches to the SVC vector.

immed is ignored by the processor. However, it can be retrieved by the exception handler to determine what service is being requested.

Note

As part of the development of the ARM assembly language, the SWI instruction has been renamed to SVC. In this release of RVCT, SWI instructions disassemble to SVC, with a comment to say that this was formerly SWI.

Condition flags

This instruction does not change the flags.

Architectures

This ARM instruction is available in all versions of the ARM architecture.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

Copyright © 2007, 2008 ARM Limited. All rights reserved.ARM DUI 0379B
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