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Preface Introduction Writing ARM Assembly Language Assembler Reference ARM and Thumb Instructions Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives Reference

B, BL, BX, BLX, and BXJ

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4.8.1. B, BL, BX, BLX, and BXJ

Branch, Branch with Link, Branch and exchange instruction set, Branch with Link and exchange instruction set, Branch and change to Jazelle state.

Syntax

op1{cond}{.W} label

op2{cond} Rm

where:

op1

is one of:

B

Branch.

BL

Branch with link.

BLX

Branch with link, and exchange instruction set.

op2

is one of:

BX

Branch and exchange instruction set.

BLX

Branch with link, and exchange instruction set.

BXJ

Branch, and change to Jazelle execution.

cond

is an optional condition code (see Conditional execution). cond is not available on all forms of this instruction, see Instruction availability and branch ranges.

.W

is an optional instruction width specifier to force the use of a 32-bit B instruction in Thumb-2. See B in Thumb-2 for details.

label

is a program-relative expression. See Register-relative and program-relative expressions for more information.

Rm

is a register containing an address to branch to.

Operation

All these instructions cause a branch to label, or to the address contained in Rm. In addition:

  • The BL and BLX instructions copy the address of the next instruction into lr (r14, the link register).

  • The BX and BLX instructions can change the processor state from ARM to Thumb, or from Thumb to ARM.

    BLX label always changes the state.

    BX Rm and BLX Rm derive the target state from bit[0] of Rm:

    • if bit[0] of Rm is 0, the processor changes to, or remains in, ARM state

    • if bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.

  • The BXJ instruction changes the processor state to Jazelle.

Instruction availability and branch ranges

Table 4.7 shows the instructions that are available in ARM and Thumb state. Instructions that are not shown in this table are not available. Notes in brackets show the first architecture version where the instruction is available.

Table 4.7. Branch instruction availability and range

InstructionARM 16-bit Thumb32-bit Thumb
B label±32MB(All)±2KB(All T)±16MB[1](All T2)
B{cond} label±32MB(All)–252 to +258(All T)±1MBa(All T2)
BL label±32MB(All)±4MB [2](All T)±16MB(All T2)
BL{cond} label±32MB(All)- --
BX RmAvailable(4T, 5)Available(All T)Use 16-bit(All T2)
BX{cond} RmAvailable(4T, 5)- --
BLX label±32MB(5)±4MB [2](5T)±16MB(All T2 except ARMv7-M)
BLX RmAvailable(5)Available(5T)Use 16-bit(All T2)
BLX{cond} RmAvailable(5)- --
BXJ RmAvailable(5J, 6)- Available(All T2 except ARMv7-M)
BXJ{cond} RmAvailable(5J, 6)- --

[1] Use .W to instruct the assembler to use this 32-bit instruction.

[2] This is an instruction pair.


Extending branch ranges

Machine-level B and BL instructions have restricted ranges from the address of the current instruction. However, you can use these instructions even if label is out of range. Often you do not know where the linker places label. When necessary, the linker adds code to enable longer branches. See Chapter 3 Using the Basic Linker Functionality in the Linker User Guide. The added code is called a veneer.

B in Thumb-2

You can use the .W width specifier to force B to generate a 32-bit instruction in Thumb-2 code.

B.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit instruction.

For forward references, B without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb instruction.

BX, BLX, and BXJ in Thumb-2EE

These instructions can be used as branches in Thumb-2EE code, but cannot be used to change state. You cannot use the op{cond} label form of these instructions in Thumb-2EE. In the register form, bit[0] of Rm must be 1, and execution continues at the target address in ThumbEE state.

Condition flags

These instructions do not change the flags.

Architectures

See Instruction availability and branch ranges for details of availability of these instructions in each architecture.

Examples

    B       loopA
    BLE     ng+8
    BL      subC
    BLLT    rtX
    BEQ     {pc}+4  ; #0x8004
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