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Preface Introduction Writing ARM Assembly Language Assembler Reference 
ARM and Thumb Instructions 
Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives ReferenceMRC, MRC2, MRRC and MRRC2
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| Home > ARM and Thumb Instructions > Coprocessor instructions > MRC, MRC2, MRRC and MRRC2 | |||
Move to ARM Register or Registers from Coprocessor.
Depending on the coprocessor, you might be able to specify various operations in addition.
{op1cond}coproc, #opcode1,Rt,CRn,CRm{, #opcode2}
{op2cond}coproc, #opcode3,Rt,Rt2,CRm
where:
op1is either
MRCorMRC2.op2is either
MRRCorMRRC2.condis an optional condition code (see Conditional execution). In ARM code,
condMRC2orMRRC2.coprocis the name of the coprocessor the instruction is for. The standard name is
p, wherennopcode1is a 3-bit coprocessor-specific opcode.
opcode2is an optional 3-bit coprocessor-specific opcode.
opcode3is a 4-bit coprocessor-specific opcode.
Rt,Rt2are ARM source registers. Do not use r15.
In
MRCandMRC2,RtAPSR_nzcv.CRn,CRmare coprocessor registers.
The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.
The MRC ARM instruction is available in all versions of the ARM architecture.
The MRC2 ARM instruction is available in ARMv5 and above.
The MRRC ARM instruction is available in ARMv6 and above, and E variants of ARMv5.
The MRRC2 ARM instruction is available in ARMv6 and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There are no 16-bit Thumb versions of these instructions.
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