ARM and Thumb Instructions

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Chapter 4. ARM and Thumb Instructions

Table of Contents

4.1. Instruction summary

4.2. Instruction width selection in Thumb

4.2.1. Instruction width specifiers, .W and .N
4.2.2. Different behavior for some instructions
4.2.3. Diagnostic warning

4.3. Memory access instructions

4.3.1. Address alignment
4.3.2. LDR and STR (immediate offset)
4.3.3. LDR and STR (register offset)
4.3.4. LDR and STR (User mode)
4.3.5. LDR (pc‑relative)
4.3.6. ADR
4.3.7. PLD and PLI
4.3.8. LDM and STM
4.3.9. PUSH and POP
4.3.10. RFE
4.3.11. SRS
4.3.12. LDREX and STREX
4.3.13. CLREX
4.3.14. SWP and SWPB

4.4. General data processing instructions

4.4.1. Flexible second operand
4.4.2. ADD, SUB, RSB, ADC, SBC, and RSC
4.4.3. SUBS pc, LR
4.4.4. AND, ORR, EOR, BIC, and ORN
4.4.5. CLZ
4.4.6. CMP and CMN
4.4.7. MOV and MVN
4.4.8. MOVT
4.4.9. TST and TEQ
4.4.10. SEL
4.4.11. REV, REV16, REVSH, and RBIT
4.4.12. ASR, LSL, LSR, ROR, and RRX
4.4.13. IT
4.4.14. SDIV and UDIV

4.5. Multiply instructions

4.5.1. MUL, MLA, and MLS
4.5.2. UMULL, UMLAL, SMULL, and SMLAL
4.5.3. SMULxy and SMLAxy
4.5.4. SMULWy and SMLAWy
4.5.5. SMLALxy
4.5.6. SMUAD{X} and SMUSD{X}
4.5.7. SMMUL, SMMLA, and SMMLS
4.5.8. SMLAD and SMLSD
4.5.9. SMLALD and SMLSLD
4.5.10. UMAAL

4.6. Saturating instructions

4.6.1. Saturating arithmetic
4.6.2. QADD, QSUB, QDADD, and QDSUB
4.6.3. SSAT and USAT

4.7. Parallel instructions

4.7.1. Parallel add and subtract
4.7.2. USAD8 and USADA8
4.7.3. SSAT16 and USAT16

4.8. Packing and unpacking instructions

4.8.1. BFC and BFI
4.8.2. SBFX and UBFX
4.8.3. SXT, SXTA, UXT, and UXTA
4.8.4. PKHBT and PKHTB

4.9. Branch instructions

4.9.1. B, BL, BX, BLX, and BXJ
4.9.2. CBZ and CBNZ
4.9.3. TBB and TBH

4.10. Coprocessor instructions

4.10.1. CDP and CDP2
4.10.2. MCR, MCR2, MCRR, and MCRR2
4.10.3. MRC, MRC2, MRRC and MRRC2
4.10.4. LDC, LDC2, STC, and STC2

4.11. Miscellaneous instructions

4.11.1. BKPT
4.11.2. SVC
4.11.3. MRS
4.11.4. MSR
4.11.5. CPS
4.11.6. SMC
4.11.7. SETEND
4.11.8. NOP, SEV, WFE, WFI, and YIELD
4.11.9. DBG, DMB, DSB, and ISB

4.12. ThumbEE instructions

4.12.1. ENTERX and LEAVEX
4.12.2. CHKA
4.12.3. HB, HBL, HBLP, and HBP

4.13. Pseudo‑instructions

4.13.1. ADRL pseudo‑instruction
4.13.2. MOV32 pseudo‑instruction
4.13.3. LDR pseudo‑instruction
4.13.4. UND pseudo‑instruction

This chapter describes the ARM^®, Thumb (32‑bit and 16‑bit), and ThumbEE instructions supported by the ARM assembler. It contains the following sections:

Some instruction sections have an Architectures subsection. Instructions that do not have an Architecture subsection are available in all versions of the ARM instruction set, and all versions of the Thumb instruction set,.

Copyright © 2007 ARM Limited. All rights reserved.	ARM DUI 0379A
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