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Preface Introduction Writing ARM Assembly Language Assembler Reference 
ARM and Thumb Instructions 
Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives ReferenceLDM and STM
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Load and Store Multiple registers. Any combination of registers r0 to r15 can be transferred in ARM state, but there are some restrictions in Thumb state.
See also PUSH and POP.
op{addr_mode}{cond}Rn{!},reglist{^}
where:
opcan be either:
LDMLoad Multiple registers
STMStore Multiple registers.
addr_modeis any one of the following:
IAIncrement address After each transfer. This is the default, and can be omitted.
IBIncrement address Before each transfer (ARM only).
DADecrement address After each transfer (ARM only).
DBDecrement address Before each transfer.
See Table 2.9 for stack oriented addressing mode suffixes.
condis an optional condition code (see Conditional execution).
Rnis the base register, the ARM register holding the initial address for the transfer.
Rn!is an optional suffix. If
!is present, the final address is written back intoRnreglistis a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range (see Examples).
^is an optional suffix, available in ARM state only. You must not use it in User mode or System mode. It has the following purposes:
If the instruction is
LDM(with any addressing mode) andreglistSPSRis copied into theCPSR. This is for returning from exception handlers. Use this only from exception modes.Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.
In 32-bit Thumb-2 instructions:
the sp cannot be in the list
the pc cannot be in the list in an
STMinstructionthe pc and lr cannot both be in the list in an
LDMinstructionthere must be two or more registers in the list.
If you write an STM or LDM instruction with only one register in reglist, the assembler automatically substitutes the equivalent STR or LDR instruction. Be aware of this when comparing disassembly listings with source code.
You can use the --diag_warning 1645 assembler command-line option to check when an instruction substitution occurs.
16-bit versions of a subset of these instructions are available in Thumb-2 code, and in Thumb code on pre-Thumb-2 processors.
The following restrictions apply to the 16-bit instructions:
all registers in
reglistRnaddr_modeIA), meaning increment address after each transferwriteback must be specified for
STMinstructionswriteback must be specified for
LDMinstructions whereRnreglist
In addition, the PUSH and POP instructions can be expressed in this form. Some forms of PUSH and POP are also 16-bit instructions. See PUSH and POP for details.
Note
These 16-bit instructions are not available in Thumb-2EE.
A load to the pc causes a branch to the instruction at the address loaded.
In ARMv4, bits[1:0] of the address loaded must be 0b00.
In ARMv5 and above:
bits[1:0] must not be 0b10
if bit[0] is 1, execution continues in Thumb state
if bit[0] is 0, execution continues in ARM state.
In ARM code or pre-Thumb-2 Thumb code, if Rnreglist! suffix:
if the instruction is
STMorSTMIAandRnreglistRnotherwise, the loaded or stored value of
Rn
In Thumb-2 code, if Rnreglist! suffix:
all 32-bit instructions are unpredictable
16-bit instructions behave in the same way as in pre-Thumb-2 Thumb code, but the use of these instructions is deprecated.
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