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Preface Introduction Writing ARM Assembly Language Assembler Reference ARM and Thumb Instructions Instruction summary Memory access instructions Address alignment LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR (User mode) LDR (pc-relative) ADR PLD, PLDW, and PLI LDM and STM PUSH and POP RFE SRS LDREX and STREX CLREX SWP and SWPB General data processing instructions Flexible second operand ADD, SUB, RSB, ADC, SBC, and RSC SUBS pc, lr AND, ORR, EOR, BIC, and ORN CLZ CMP and CMN MOV and MVN MOVT TST and TEQ SEL REV, REV16, REVSH, and RBIT ASR, LSL, LSR, ROR, and RRX SDIV and UDIV Multiply instructions MUL, MLA, and MLS UMULL, UMLAL, SMULL, and SMLAL SMULxy and SMLAxy SMULWy and SMLAWy SMLALxy SMUAD{X} and SMUSD{X} SMMUL, SMMLA, and SMMLS SMLAD and SMLSD SMLALD and SMLSLD UMAAL Saturating instructions Saturating arithmetic QADD, QSUB, QDADD, and QDSUB SSAT and USAT Parallel instructions Parallel add and subtract USAD8 and USADA8 SSAT16 and USAT16 Packing and unpacking instructions BFC and BFI SBFX and UBFX SXT, SXTA, UXT, and UXTA PKHBT and PKHTB Branch and control instructions B, BL, BX, BLX, and BXJ IT CBZ and CBNZ TBB and TBH Coprocessor instructions CDP and CDP2 MCR, MCR2, MCRR, and MCRR2 MRC, MRC2, MRRC and MRRC2 LDC, LDC2, STC, and STC2 Miscellaneous instructions BKPT SVC MRS MSR CPS SMC SETEND NOP, SEV, WFE, WFI, and YIELD DBG, DMB, DSB, and ISB Instruction width selection in Thumb Instruction width specifiers, .W and .N Different behavior for some instructions Diagnostic warning ThumbEE instructions ENTERX and LEAVEX CHKA HB, HBL, HBLP, and HBP Pseudo-instructions ADRL pseudo-instruction MOV32 pseudo-instruction LDR pseudo-instruction UND pseudo-instruction Directives Reference

UMULL, UMLAL, SMULL, and SMLAL

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4.4.2. UMULL, UMLAL, SMULL, and SMLAL

Signed and Unsigned Long Multiply, with optional Accumulate, with 32-bit operands, and 64-bit result and accumulator.

Syntax

Op{S}{cond} RdLo, RdHi, Rn, Rm

where:

Op

is one of UMULL, UMLAL, SMULL, or SMLAL.

S

is an optional suffix available in ARM state only. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

cond

is an optional condition code (see Conditional execution).

RdLo, RdHi

are the destination registers. For UMLAL and SMLAL they also hold the accumulating value. RdLo and RdHi must be different registers

Rn, Rm

are ARM registers holding the operands.

Do not use r15 for RdHi, RdLo, Rn, or Rm.

Usage

The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, and adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.

The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, and adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo.

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • do not affect the C or V flags.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no 16-bit Thumb versions of these instructions.

Examples

    UMULL       r0, r4, r5, r6
    UMLALS      r4, r5, r3, r8
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