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RealView Assembler User's Guide
Preface Introduction Writing ARM Assembly Language Assembler Reference Command syntax
Obtaining a list of available options Specifying command‑line options with an environm AAPCS Floating‑point model Memory access attributes Pre‑executing a SET directive Splitting long LDMs and STMs Listing output to a file Project template options Controlling the output of diagnostic messages Controlling exception table generation Format of source lines Predefined register and coprocessor names Predeclared register names Predeclared extension register names Predeclared coprocessor names Built‑in variables and constants Symbols Symbol naming rules Variables Numeric constants Assembly time substitution of variables Labels Local labels Expressions, literals, and operators String expressions String literals Numeric expressions Numeric literals Floating‑point literals Register‑relative and program‑relative express Logical expressions Logical literals Operator precedence Unary operators Binary operators Diagnostic messages Interlocks IT block generation Thumb branch target alignment Using the C preprocessor ARM and Thumb Instructions Directives ReferenceSplitting long LDMs and STMs
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| Home > Assembler Reference > Command syntax > Splitting long LDMs and STMs | |||
Use the following option to instruct the assembler to fault LDM and STM instructions with large numbers of registers:
‑‑split_ldm
This option faults LDM and STM instructions if the maximum number of registers transferred exceeds:
five, for all
STMs, and forLDMs that do not load the PCfour, for
LDMs that load the PC.
Avoiding large multiple register transfers can reduce interrupt latency on ARM systems that:
do not have a cache or a write buffer (for example, a cacheless ARM7TDMI)
use zero wait‑state, 32‑bit memory.
Also, avoiding large multiple register transfers:
always increases code size.
has no significant benefit for cached systems or processors with a write buffer.
has no benefit for systems without zero wait‑state memory, or for systems with slow peripheral devices. Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access. This is typically much greater than the latency introduced by multiple register transfers.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0379A |
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