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Overview of the ARM Architecture
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Assembler User Guide
Current Program Status Register
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| Home > Overview of the ARM Architecture > Current Program Status Register | |||
The Current Program Status Register (CPSR) holds:
the APSR flags
the current processor mode
interrupt disable flags
current processor state (ARM, Thumb, ThumbEE, or Jazelle®)
endianness state (on ARMv4T and later)
execution state bits for the IT block (on ARMv6T2 and later).
The execution state bits control conditional execution in the IT block.
Only the APSR flags are accessible in all modes. The endianness
bit (E) of the CPSR is accessible only in privileged software execution.
It can be read by MRS and written by MSR,
but SETEND is the preferred instruction to write to
the E bit.
The execution state bits for the IT block (IT[1:0]), Jazelle
bit (J), and Thumb bit (T) can be accessed by MRS only
in Debug state.
See also- Concepts
- Reference
Assembler Reference:
| Copyright © 2007-2008, 2011-2012 ARM. All rights reserved. | ARM DUI 0379D |
| Non-Confidential | ID062912 |
 PDF version | |
| Home > Overview of the ARM Architecture > Current Program Status Register |
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