Load immediate 32-bit values to a
register using LDR Rd, =const
The LDR Rd,=const pseudo-instruction
can construct any 32-bit numeric value in a single instruction.
You can use this pseudo-instruction to generate constants that are
out of range of the MOV and MVN instructions.
The LDR pseudo-instruction generates the most
efficient single instruction for the specified immediate value:
If the immediate value can be constructed with a
single MOV or MVN instruction, the assembler
generates the appropriate instruction.
If the immediate value cannot be constructed with
a single MOV or MVN instruction, the assembler:
places the value in a literal pool (a
portion of memory embedded in the code to hold constant values)
generates an LDR instruction with a
PC-relative address that reads the constant from the literal pool.
For
example:
LDR rn, [pc, #offset to literal pool]
; load register n with one word
; from the address [pc + offset]
You must ensure that there is a literal pool within range
of the LDR instruction generated by the assembler.
This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.
ARM websites use two types of cookie: (1) those that enable the site to function and perform as required; and (2) analytical cookies which anonymously track visitors only while using the site. If you are not happy with this use of these cookies please review our Privacy Policy to learn how they can be disabled. By disabling cookies some features of the site will not work.