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Preface Introduction Writing ARM Assembly Language
Introduction Overview of the ARM architecture Architecture versions ARM, Thumb, Thumb‑2, and Thumb‑2EE instruction ARM, Thumb, and ThumbEE state Processor mode Registers Instruction set overview Instruction capabilities Structure of assembly language modules Layout of assembly language source files An example ARM assembly language module Calling subroutines Conditional execution The ALU status flags Conditional execution Using conditional execution Example of the use of conditional execution The Q flag Loading constants into registers Direct loading with MOV and MVN Loading with MOV32 Loading with LDR Rd, =const Loading addresses into registers Direct loading with ADR and ADRL Loading addresses with LDR Rd, =label Load and store multiple register instructions Load and store multiple instructions available in Implementing stacks with LDM and STM Block copy with LDM and STM Using macros Test‑and‑branch macro example Unsigned integer division macro example Using frame directives Assembly language changes Assembler Reference ARM and Thumb Instructions Directives ReferenceRegisters
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ARM processors have 37 registers. The registers are arranged in partially overlapping banks. There is a different register bank for each processor mode. The banked registers give rapid context switching for dealing with processor exceptions and privileged operations. See ARM Architecture Reference Manual for a detailed description of how registers are banked.
The following registers are available:
Fifteen general‑purpose registers are visible at any one time, depending on the current processor mode, as r0, r1, ... , r13, r14.
r13 is the stack pointer (sp). The C and C++ compilers always use r13 as the stack pointer. In Thumb-2 sp is strictly defined as the stack pointer, so many instructions that are not useful in stack manipulation are unpredictable if r13 is used. Use of sp as a general purpose register is discouraged.
In User mode, r14 is used as a link register (lr) to store the return address when a subroutine call is made. It can also be used as a general‑purpose register if the return address is stored on the stack.
In the exception handling modes, r14 holds the return address for the exception, or a subroutine return address if subroutine calls are executed within an exception. r14 can be used as a general‑purpose register if the return address is stored on the stack.
The Program Counter is accessed as r15 (or pc). It is incremented by one word (four bytes) for each instruction in ARM state, or by the size of the instruction executed in Thumb state. Branch instructions load the destination address into pc. You can also load the PC directly using data operation instructions. For example, to return from a subroutine, you can copy the link register into the PC using:
MOV pc,lr
During execution, r15 (pc) does not contain the address of the currently executing instruction. The address of the currently executing instruction is typically pc–8 for ARM, or pc–4 for Thumb.
The APSR holds copies of the Arithmetic Logic Unit (ALU) status flags. They are used to determine whether conditional instructions are executed or not. See Conditional execution for more information.
On ARMv5TE, and ARMv6 and above, the APSR also holds the Q flag (see The ALU status flags).
On ARMv6 and above, the APSR also holds the GE flags (see Parallel add and subtract).
These flags are accessible in all modes, using MSR and MRS instructions. See MRS and MSR for details.
The CPSR holds:
the APSR flags
the current processor mode
interrupt disable flags.
On Thumb‑capable or Jazelle®‑capable processors, the CPSR also holds the current processor state (ARM, Thumb, ThumbEE, or Jazelle).
On ARMv6T2 and above, Thumb‑2 introduces new state bits to the CPSR. These are used by the IT instruction to control conditional execution of the IT block (see IT).
Only the APSR flags are accessible in all modes. The remaining bits of the CPSR are accessible only in privileged modes, using MSR and MRS instructions. See MRS and MSR for details.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0379A |
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