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RealView Assembler User's Guide
Preface Introduction Writing ARM Assembly Language
Introduction Overview of the ARM architecture Architecture versions ARM, Thumb, Thumb‑2, and Thumb‑2EE instruction ARM, Thumb, and ThumbEE state Processor mode Registers Instruction set overview Instruction capabilities Structure of assembly language modules Layout of assembly language source files An example ARM assembly language module Calling subroutines Conditional execution The ALU status flags Conditional execution Using conditional execution Example of the use of conditional execution The Q flag Loading constants into registers Direct loading with MOV and MVN Loading with MOV32 Loading with LDR Rd, =const Loading addresses into registers Direct loading with ADR and ADRL Loading addresses with LDR Rd, =label Load and store multiple register instructions Load and store multiple instructions available in Implementing stacks with LDM and STM Block copy with LDM and STM Using macros Test‑and‑branch macro example Unsigned integer division macro example Using frame directives Assembly language changes Assembler Reference ARM and Thumb Instructions Directives ReferenceLoad and store multiple instructions available in ARM and Thumb
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| Home > Writing ARM Assembly Language > Load and store multiple register instructions > Load and store multiple instructions available in ARM and Thumb | |||
The following instructions are available in both ARM and Thumb instruction sets:
LDMLoad Multiple registers.
STMStore Multiple registers.
PUSHStore multiple registers onto the stack and update the stack pointer.
POPLoad multiple registers off the stack, and update the stack pointer.
In LDM and STM instructions:
The list of registers loaded or stored can include:
in ARM instructions, any or all of r0‑r15
in 32‑bit Thumb‑2 instructions, any or all of r0‑r12, and optionally r14 or r15 with some restrictions
in 16‑bit Thumb and Thumb‑2 instructions, any or all of r0‑r7.
The address can be:
incremented after each transfer
incremented before each transfer (ARM instructions only)
decremented after each transfer (ARM instructions only)
decremented before each transfer (not in 16‑bit Thumb).
The base register can be either:
updated to point to the next block of data in memory
left as it was before the instruction (not in 16‑bit Thumb).
When the base register is updated to point to the next block in memory, this is called writeback, that is, the adjusted address is written back to the base register.
In PUSH and POP instructions:
The stack pointer (r13) is the base register, and is always updated.
The address is incremented after each transfer in
POPinstructions, and decremented before each transfer inPUSHinstructions.The list of registers loaded or stored can include:
in ARM instructions, any or all of r0‑r15
in 32‑bit Thumb‑2 instructions, any or all of r0‑r12, and optionally r14 or r15 with some restrictions
in 16‑bit Thumb‑2 and Thumb instructions, any or all of r0‑r7, and optionally r14 (
PUSHonly) or r15 (POPonly).
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0379A |
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