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Overview of the Assembler Overview of the ARM Architecture Structure of Assembly Language Modules 
Writing ARM Assembly Language Unified Assembler Language Subroutines calls Load immediates into registers Load immediate values using MOV and MVN Load 32-bit values to a register using MOV32 Load immediate 32-bit values to a register using L Literal pools Load addresses into registers Load addresses to a register using ADR Load addresses to a register using ADRL Load addresses to a register using LDR Rd, =label Other ways to Load and store registers Load and store multiple register instructions Load and store multiple instructions available in Stack implementation using LDM and STM Stack operations for nested subroutines Block copy with LDM and STM Memory accesses Read-Modify-Write procedure Optional hash Use of macros Test-and-branch macro example Unsigned integer division macro example Instruction and directive relocations Symbol versions Frame directives Exception tables and Unwind tables Assembly language changes after RVCTv2.1 Condition Codes Using the Assembler Symbols, Literals, Expressions, and Operators VFP ProgrammingLoad and store multiple instructions available in ARM and Thumb
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The following instructions are available in both ARM and Thumb instruction sets:
LDMLoad Multiple registers.
STMStore Multiple registers.
PUSHStore multiple registers onto the stack and update the stack pointer.
POPLoad multiple registers off the stack, and update the stack pointer.
In LDM and STM instructions:
The list of registers loaded or stored can include:
in ARM instructions, any or all of R0-R12, SP, LR, and PC
in 32-bit Thumb instructions, any or all of R0-R12, and optionally LR or PC (
LDMonly) with some restrictionsin 16-bit Thumb instructions, any or all of R0-R7.
The address can be:
incremented after each transfer
incremented before each transfer (ARM instructions only)
decremented after each transfer (ARM instructions only)
decremented before each transfer (not in 16-bit Thumb).
The base register can be either:
updated to point to the next block of data in memory
left as it was before the instruction.
When the base register is updated to point to the next block in memory, this is called writeback, that is, the adjusted address is written back to the base register.
In PUSH and POP instructions:
The stack pointer (SP) is the base register, and is always updated.
The address is incremented after each transfer in
POPinstructions, and decremented before each transfer inPUSHinstructions.The list of registers loaded or stored can include:
in ARM instructions, any or all of R0-R12, SP, LR, and PC
in 32-bit Thumb instructions, any or all of R0-R12, and optionally LR or PC (
POPonly) with some restrictionsin 16-bit Thumb instructions, any or all of R0-R7, and optionally LR (
PUSHonly) or PC (POPonly).
Note
Use of SP in the list of registers in any of these ARM instructions is deprecated.
ARM STM and PUSH instructions that use PC in the list of registers, and ARM LDM and POP instructions that use both PC and LR in the list of registers are deprecated.
See also| Copyright © 2007-2008, 2011 ARM. All rights reserved. | ARM DUI 0379C |
| Non-Confidential | ID061811 |
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