2.4.2. Conditional execution
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. This condition is encoded in ARM instructions, and encoded in a preceding IT instruction for Thumb-2 instructions. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 2.2 shows the condition codes that you can use.
On Thumb processors without Thumb-2, the {cond} field is only permitted on certain branch instructions.
Table 2.2 also shows the relationship between condition code suffixes and the N, Z, C and V flags.
Table 2.2. Condition code suffixes
| Suffix | Flags | Meaning |
|---|
EQ | Z set | Equal |
NE | Z clear | Not equal |
CS/HS | C set | Higher or same (unsigned >= ) |
CC/LO | C clear | Lower (unsigned < ) |
MI | N set | Negative |
PL | N clear | Positive or zero |
VS | V set | Overflow |
VC | V clear | No overflow |
HI | C set and Z clear | Higher (unsigned > ) |
LS | C clear or Z set | Lower or same (unsigned <= ) |
GE | N and V the same | Signed >= |
LT | N and V differ | Signed < |
GT | Z clear, N and V the same | Signed > |
LE | Z set, N and V differ | Signed <= |
AL | Any | Always. This suffix is normally omitted. |
Example 2.3 shows an example of conditional execution.
Example 2.3.
ADD r0, r1, r2 ; r0 = r1 + r2, don't update flags
ADDS r0, r1, r2 ; r0 = r1 + r2, and update flags
ADDSCS r0, r1, r2 ; If C flag set then r0 = r1 + r2, and update flags
CMP r0, r1 ; update flags based on r0‑r1.