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Preface Introduction Writing ARM Assembly Language
Introduction Overview of the ARM architecture Architecture versions ARM, Thumb, Thumb‑2, and Thumb‑2EE instruction ARM, Thumb, and ThumbEE state Processor mode Registers Instruction set overview Instruction capabilities Structure of assembly language modules Layout of assembly language source files An example ARM assembly language module Calling subroutines Conditional execution The ALU status flags Conditional execution Using conditional execution Example of the use of conditional execution The Q flag Loading constants into registers Direct loading with MOV and MVN Loading with MOV32 Loading with LDR Rd, =const Loading addresses into registers Direct loading with ADR and ADRL Loading addresses with LDR Rd, =label Load and store multiple register instructions Load and store multiple instructions available in Implementing stacks with LDM and STM Block copy with LDM and STM Using macros Test‑and‑branch macro example Unsigned integer division macro example Using frame directives Assembly language changes Assembler Reference ARM and Thumb Instructions Directives ReferenceOverview of the ARM architecture
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This section gives a brief overview of the ARM architecture.
ARM processors are typical of RISC processors in that they implement a load/store architecture. Only load and store instructions can access memory. Data processing instructions operate on register contents only.
This section describes:
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0379A |
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