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Preface Introduction Writing ARM Assembly Language
Introduction Overview of the ARM architecture Architecture versions ARM, Thumb, Thumb‑2, and Thumb‑2EE instruction ARM, Thumb, and ThumbEE state Processor mode Registers Instruction set overview Instruction capabilities Structure of assembly language modules Layout of assembly language source files An example ARM assembly language module Calling subroutines Conditional execution The ALU status flags Conditional execution Using conditional execution Example of the use of conditional execution The Q flag Loading constants into registers Direct loading with MOV and MVN Loading with MOV32 Loading with LDR Rd, =const Loading addresses into registers Direct loading with ADR and ADRL Loading addresses with LDR Rd, =label Load and store multiple register instructions Load and store multiple instructions available in Implementing stacks with LDM and STM Block copy with LDM and STM Using macros Test‑and‑branch macro example Unsigned integer division macro example Using frame directives Assembly language changes Assembler Reference ARM and Thumb Instructions Directives ReferenceBlock copy with LDM and STM
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| Home > Writing ARM Assembly Language > Load and store multiple register instructions > Block copy with LDM and STM | |||
Example 2.8 is an ARM code routine that copies a set of words from a source location to a destination by copying a single word at a time.
Example 2.8. Block copy without LDM and STM
AREA Word, CODE, READONLY ; name this block of code
num EQU 20 ; set number of words to be copied
ENTRY ; mark the first instruction called
start
LDR r0, =src ; r0 = pointer to source block
LDR r1, =dst ; r1 = pointer to destination block
MOV r2, #num ; r2 = number of words to copy
wordcopy
LDR r3, [r0], #4 ; load a word from the source and
STR r3, [r1], #4 ; store it to the destination
SUBS r2, r2, #1 ; decrement the counter
BNE wordcopy ; ... copy more
stop
MOV r0, #0x18 ; angel_SWIreason_ReportException
LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit
SVC #0x123456 ; ARM semihosting (formerly SWI)
AREA BlockData, DATA, READWRITE
src DCD 1,2,3,4,5,6,7,8,1,2,3,4,5,6,7,8,1,2,3,4
dst DCD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
END
This module can be made more efficient by using LDM and STM for as much of the copying as possible. Eight is a sensible number of words to transfer at a time, given the number of registers that the ARM has. The number of eight‑word multiples in the block to be copied can be found (if r2 = number of words to be copied) using:
MOVS r3, r2, LSR #3 ; number of eight word multiples
This value can be used to control the number of iterations through a loop that copies eight words per iteration. When there are less than eight words left, the number of words left can be found (assuming that r2 has not been corrupted) using:
ANDS r2, r2, #7
Example 2.9 lists the block copy module rewritten to use LDM and STM for copying.
Example 2.9. Block copy using LDM and STM
AREA Block, CODE, READONLY ; name this block of code
num EQU 20 ; set number of words to be copied
ENTRY ; mark the first instruction called
start
LDR r0, =src ; r0 = pointer to source block
LDR r1, =dst ; r1 = pointer to destination block
MOV r2, #num ; r2 = number of words to copy
MOV sp, #0x400 ; Set up stack pointer (r13)
blockcopy
MOVS r3,r2, LSR #3 ; Number of eight word multiples
BEQ copywords ; Less than eight words to move?
PUSH {r4‑r11} ; Save some working registers
octcopy
LDM r0!, {r4‑r11} ; Load 8 words from the source
STM r1!, {r4‑r11} ; and put them at the destination
SUBS r3, r3, #1 ; Decrement the counter
BNE octcopy ; ... copy more
POP {r4‑r11} ; Don't need these now ‑ restore
; originals
copywords
ANDS r2, r2, #7 ; Number of odd words to copy
BEQ stop ; No words left to copy?
wordcopy
LDR r3, [r0], #4 ; Load a word from the source and
STR r3, [r1], #4 ; store it to the destination
SUBS r2, r2, #1 ; Decrement the counter
BNE wordcopy ; ... copy more
stop
MOV r0, #0x18 ; angel_SWIreason_ReportException
LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit
SVC #0x123456 ; ARM semihosting (formerly SWI)
AREA BlockData, DATA, READWRITE
src DCD 1,2,3,4,5,6,7,8,1,2,3,4,5,6,7,8,1,2,3,4
dst DCD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
END
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0379A |
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