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ARM: Cortex M7 DMA linked lists transfers are failing

Information in this knowledgebase article applies to:

  • Atmel V70/71 Cortex M7 devices


I am using linked lists to control DMA transfers using the Atmel XDMAC peripheral on a Cortex M7 processor. I have declared the linked list structure as described in the device data sheet and have initialized the structure in code. However, the DMA controller does not seem to read the linked list descriptors correctly and my DMA transfers are not occurring. What is wrong?


The Atmel Cortex M7 devices utilize cache memory to speed up processor execution. Many code examples initialize the instruction and data cache in the first few lines of application code. If the linked list structure is initialized after the data cache is enabled, then the initialization data will remain in cache until it is evicted which may not happen before the DMA is enabled. If this is the case, the DMA controller will try to read the initialization data from the main memory address assigned to the linked lists and not from the cache. Since the initialization data is still in cache memory, it is not available to be read from main memory. As a result, the DMA linked list transfer will fail.


The instructions SCB_CleanDCache () and SCB_CleanInvalidateDCache () in core_cm7.h will force the data cache to be flushed to main memory. It is recommended to use one of these instructions after initializing the DMA linked list structure. The other option is to initialize the linked list structure prior to enabling the data cache. In either case, the descriptors for the DMA linked lists structure will be in main memory and the DMA linked list transfers can occur.


Last Reviewed: Tuesday, September 29, 2015

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