ARM: STM32F4xx_DFP: problems with 3 byte reception in I2C master mode
Information in this knowledgebase article applies to:
When I after a 2-byte master receive operation perform another master receive operation, that shall receive more than 2 bytes, e. g:
I2C1_MasterReceive (0x50, &buffer, 2, 0); I2C1_MasterReceive (0x50, &buffer, 3, 0);
the driver fails to handle this correctly.
The driver has problems with 3 byte reception and I2C_CR1_POS bit handling in master mode.
To correct this, modifications in the I2C_EV_IRQHandler()
interrupt handler are required.
after making a backup of the original file and removing the write protection from it. Then build the project again.
STM32F4xx_DFP versions released after version 2.5.0 will also contain this or an even newer driver, that corrects the problem.
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Last Reviewed: Monday, July 6, 2015
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