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ARM: CORTEX-M3 DEVICE SIMULATION RESULT DIFFERS FROM REAL HARDWARE


Information in this article applies to:

  • MDK-ARM All Versions

SYMPTOMS

While toggling an I/O pin on a Cortex-M3 device, I noticed that the target hardware executes slower than simulation.

Why is the timing different?

CAUSE

The Cortex-M3 simulation is cycle accurate with the following exceptions:

  • Memory accelerators are not simulated (zero latency is assumed).
  • When executing code from the system bus (like SRAM), the instruction stalls due to reading and writing data to the system bus is not taken into account.
  • Some combination of instructions (LDR,STR, etc., branch folding) can lead to reduced cycles. This is not simulated.

In general, this means that the simulator will execute a bit faster than hardware.

CONCLUSION

Simulation will differ slightly from the hardware regarding cycles due to:

  • Some Cortex-M features are not fully simulated
  • Different vendor-specific memory interface implementations which are also not simulated.

Last Reviewed: Thursday, October 22, 2015


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