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ARMCC: EXECUTION OF SPECIAL INSTRUCTIONS WITH OPTIMIZE 3


Information in this support solution applies to:

  • RealView MDK-ARM V3.50 and below
  • Cortex-M0, Cortex-M3 cores

SYMPTOM

The execution of instructions seems to be out of sequence. This causes strange effects with special instructions such as WFI or WFE.

CAUSE

When using the highest Compiler optimization level 3, the compiler rearranges instructions. Therefore a special instructions such as WFI or WFE may be re-arranged.

EXAMPLE

The C code looks like:

SysCtrl |= 0x00000004;   /* set DEEPSLEEP bit */
__wfi();                 /* Request Wait For Interrupt */

The compiler generates with optimization level 3 the following code:

LDR      r0,[r1,#0x00]           ;Read
WFI                              ;WFI
ORR      r0,r0,#0x04             ;Modify
STR      r0,[r1,#0x00]           ;Write

But expected is this code:

LDR      r0,[r1,#0x00]           ;Read
ORR      r0,r0,#0x04             ;Modify
STR      r0,[r1,#0x00]           ;Write
WFI                              ;WFI

RESOLUTION

Insert the __force_stores() intrinsic function to ensure that write operations are completed before a special instruction is executed.

SysCtrl |= 0x00000004;   /* set DEEPSLEEP bit */
__force_stores();        /* ensure store operation is completed */
__wfi();                 /* Request Wait For Interrupt */

Last Reviewed: Tuesday, March 24, 2009


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