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Information in this support solution applies to:

  • Cortex-M3 / Cortex-M3 with ETM
  • RealView MDK V3.24 or before


The Cortex-M3 CPU Core has a problem when executing LDRD with the base register in the list of the form LDRD Ra, Rb, [Ra, #imm]. The instruction may not complete after the load of the first destination register when an interrupt occurs during execution of the instruction.

Is this a serious problem that I need to be concerned with? Are the instructions actually generated by the RealView Compiler?


Yes, the instructions are generated by the RealView Compiler Version V3.1.0.940 or before.  RealView Compiler Versions and later no longer generate this sequence. RealView Compiler update(V3.1.0.942) is part of RealView MDK V3.30 and higher.

It actually depends on the device whether the instruction may cause problems or not. For most devices the instruction execution is correct when code is fetched from on-chip Flash ROM. Check with the silicon vendor for clarification of the errata.

For existing code you may check the image with the attached fromelf and scanning tool for the erroneous instruction. If the erroneous code is detected in the text file you will see the warning:

WARNING: Found 1 instances of LDRD code which are
susceptible to the Cortex-M3 LDRD erratum (erratum #602117)

To automate the check, apply the following changes to your µVision project:

  • Download the attachment of this knowledgebase article and copy CM3Errata602117.exe and fromelf.exe to the folder .\Keil\ARM\BIN31
  • In µVision add the following command under Options for Target - User - Run User Programs After Build/Rebuild - Run #1:
    fromelf -c #L --output @L.txt
  • Under Options for Target - User - Run User Programs After Build/Rebuild - Run #2 add the command:
    CM3Errata602117 @L.txt

With these changes the check is performed every time you build your target application.



Request the files attached to this knowledgebase article.

Last Reviewed: Monday, July 2, 2018

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