CARM: ATOMIC EXECUTION SEQUENCES

Information in this article applies to:

• CARM All Versions

QUESTION

I want to create ATOMIC instruction sequences that are interrupt protected. But once the startup code sets the ARM CPU into USER operation mode, the CPSR can no longer be modified.

Is there another method to implement ATOMIC instruction sequences? Can you give me a guideline?

ANSWER

The ARM CPU provides an SWI (Software Interrupt) instruction. Software Interrupts store the CPSR (Current Program Status Register) and disable IRQ interrupts. Therefore an SWI function is protected against interrupts.

The Keil CARM Compiler provides an efficient SWI interrupt handler. The definition of software interrupt functions (in this example an ATOMIC AND operation) is as shown below:

// Atomic AND operation: *val &= mask
unsigned int AImsk (unsigned int *val, unsigned int mask) __swi(8)  {
  return (*val &= mask);
}

As explained above, SWI functions automatically disable the IRQ interrupt. If you need to block the FIQ interrupt also, you may write the SWI function in ARM mode and use the MSR CPSR_c instruction to block the FIQ interrupt. The following routine shows this:

// Atomic AND operation: *val &= mask
unsigned int AImsk (unsigned int *val, unsigned int mask) __arm __swi(8)  {
  asm {MSR CPSR_c, #0xd3}    // disable FIQ
  return (*val &= mask);
}

To use the asm {MSR CPSR_c, #0xd3} instruction, you must translate the function in ARM mode using the __arm function attribute. In Thumb mode, the instruction is not available and generates a syntax error.

MORE INFORMATION

• Refer to __swi: Software Interrupt in the CARM User's Guide.

SEE ALSO

• CARM: NESTING INTERRUPTS
• ARM: SPORADIC INTERRUPT PROBLEMS
• ARTX: USING SWI_VEC.S WITH ARTX-ARM

FORUM THREADS

The following Discussion Forum threads may provide information related to this topic.

• LPC2129 Fast Interrupt and Watchdog Happenings
• Inline asm error C-197 when disabling interrupt...

Last Reviewed: Tuesday, June 28, 2005